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U/UF/M/MF vector test macro #37

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marcfedorow wants to merge 2 commits into from
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U/UF/M/MF vector test macro #37

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5eb62ad
add macro for vector test to not switch to U-mode after initialization
EricCheng2222 Feb 17, 2022
abe295c
Create different macroses for vector init
marcfedorow Mar 28, 2022
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49 changes: 49 additions & 0 deletions p/riscv_test.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,21 @@
RVTEST_VECTOR_ENABLE; \
.endm

#define RVTEST_RV64MV \
.macro init; \
RVTEST_MVECTOR_ENABLE; \
.endm

#define RVTEST_RV64UFV \
.macro init; \
RVTEST_FP_VECTOR_ENABLE; \
.endm

#define RVTEST_RV64MFV \
.macro init; \
RVTEST_FP_MVECTOR_ENABLE; \
.endm

#define RVTEST_RV32U \
.macro init; \
.endm
Expand All @@ -37,6 +52,21 @@
RVTEST_VECTOR_ENABLE; \
.endm

#define RVTEST_RV32MV \
.macro init; \
RVTEST_MVECTOR_ENABLE; \
.endm

#define RVTEST_RV32UFV \
.macro init; \
RVTEST_FP_VECTOR_ENABLE; \
.endm

#define RVTEST_RV32MFV \
.macro init; \
RVTEST_FP_MVECTOR_ENABLE; \
.endm

#define RVTEST_RV64M \
.macro init; \
RVTEST_ENABLE_MACHINE; \
Expand Down Expand Up @@ -139,12 +169,31 @@
csrwi fcsr, 0

#define RVTEST_VECTOR_ENABLE \
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)); \
csrs mstatus, a0; \
csrwi vcsr, 0;

#define RVTEST_MVECTOR_ENABLE \
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \
(MSTATUS_MPP); \
csrs mstatus, a0; \
csrwi vcsr, 0;

#define RVTEST_FP_VECTOR_ENABLE \
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \
(MSTATUS_FS & (MSTATUS_FS >> 1)); \
csrs mstatus, a0; \
csrwi fcsr, 0; \
csrwi vcsr, 0;

#define RVTEST_FP_MVECTOR_ENABLE \
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \
(MSTATUS_FS & (MSTATUS_FS >> 1)) | \
(MSTATUS_MPP); \
csrs mstatus, a0; \
csrwi fcsr, 0; \
csrwi vcsr, 0;

#define RISCV_MULTICORE_DISABLE \
csrr a0, mhartid; \
1: bnez a0, 1b
Expand Down