Support Q-extension

gcc/ChangeLog

@@ -1,3 +1,37 @@
+2017-08-03  Kito Cheng  <[email protected]>
+	    Monk Chiang  <[email protected]>
+
+	* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
+	Support parsing rv32e*.
+	* config.gcc (riscv*-*-elf*): Support rv32e*.
+	* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
+	__riscv_32e for rv32e*.
+	* config/riscv/riscv.c (riscv_compute_frame_info): Support rv32e.
+	(riscv_conditional_register_usage): Ditto.
+	* config/riscv/riscv.h (BIGGEST_ALIGNMENT): Ditto.
+	(GP_REG_LAST): Ditto.
+	(STACK_BOUNDARY): Ditto.
+	(MAX_ARGS_IN_REGISTERS): Ditto.
+	(RISCV_STACK_ALIGN): Ditto.
+	* config/riscv/riscv.opt (RVE): Add RVE mask.
+
+2017-05-18  Andrew Waterman  <[email protected]>
+
+	* config/riscv/riscv.c (riscv_option_override): Conditionally set
+	TARGET_STRICT_ALIGN based upon -mtune argument.
+
+2017-05-12  Kito Cheng  <[email protected]>
+
+	* config/riscv/riscv.c (riscv_legitimize_move): Handle
+	non-legitimate address.
+
+2017-05-09  Palmer Dabbelt  <[email protected]>
+
+	* config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
+	* config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
+	mark as a sign-extending load.
+	(local_pic_load_u): Define.
+
 2017-07-31  Segher Boessenkool  <[email protected]>
 
 	* config/rs6000/rs6000.c (enum rs6000_reg_type): Delete trailing comma.

gcc/common/config/riscv/riscv-common.c

@@ -52,6 +52,11 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
       *flags |= MASK_ATOMIC;
       *flags |= MASK_HARD_FLOAT;
       *flags |= MASK_DOUBLE_FLOAT;
+      if (*p == 'q')
+	{
+	  *flags |= MASK_QUAD_FLOAT;
+	  p++;
+	}
     }
   else if (*p == 'i')
     {
@@ -74,9 +79,34 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
 	    {
 	      *flags |= MASK_DOUBLE_FLOAT;
 	      p++;
+	      if (*p == 'q')
+		{
+		  *flags |= MASK_QUAD_FLOAT;
+		  p++;
+		}
 	    }
 	}
     }
+  else if (*p == 'e')
+    {
+      p++;
+
+      *flags |= MASK_RVE;
+
+      if (*flags & MASK_64BIT)
+	{
+	  error ("RV64E is not a valid base ISA");
+	  return;
+	}
+
+      *flags &= ~MASK_MUL;
+      if (*p == 'm')
+	*flags |= MASK_MUL, p++;
+
+      *flags &= ~MASK_ATOMIC;
+      if (*p == 'a')
+	*flags |= MASK_ATOMIC, p++;
+    }
   else
     {
       error_at (loc, "-march=%s: invalid ISA string", isa);

gcc/config.gcc

@@ -4016,19 +4016,20 @@ case "${target}" in
 
 		# Infer arch from --with-arch, --target, and --with-abi.
 		case "${with_arch}" in
-		rv32i* | rv32g* | rv64i* | rv64g*)
+		rv32e* | rv32i* | rv32g* | rv64i* | rv64g*)
 			# OK.
 			;;
 		"")
 			# Infer XLEN, but otherwise assume GC.
 			case "${with_abi}" in
 			ilp32 | ilp32f | ilp32d) with_arch="rv32gc" ;;
 			lp64 | lp64f | lp64d) with_arch="rv64gc" ;;
+			lp64q) with_arch="rv64gqc" ;;
 			*) with_arch="rv${xlen}gc" ;;
 			esac
 			;;
 		*)
-			echo "--with-arch=${with_arch} is not supported.  The argument must begin with rv32i, rv32g, rv64i, or rv64g." 1>&2
+			echo "--with-arch=${with_arch} is not supported.  The argument must begin with rv32e, rv32i, rv32g, rv64i, or rv64g." 1>&2
 			exit 1
 			;;
 		esac
@@ -4037,12 +4038,13 @@ case "${target}" in
 		# pick a default based on the ISA, preferring soft-float
 		# unless the D extension is present.
 		case "${with_abi}" in
-		ilp32 | ilp32f | ilp32d | lp64 | lp64f | lp64d)
+		ilp32 | ilp32f | ilp32d | lp64 | lp64f | lp64d | lp64q)
 			;;
 		"")
 			case "${with_arch}" in
 			rv32*d* | rv32g*) with_abi=ilp32d ;;
 			rv32*) with_abi=ilp32 ;;
+			rv64*q* ) with_abi=lp64q ;;
 			rv64*d* | rv64g*) with_abi=lp64d ;;
 			rv64*) with_abi=lp64 ;;
 			esac
@@ -4060,7 +4062,8 @@ case "${target}" in
 		| ilp32d,rv32*d* | ilp32d,rv32g* \
 		| lp64,rv64* \
 		| lp64f,rv64*f* | lp64f,rv64g* \
-		| lp64d,rv64*d* | lp64d,rv64g*)
+		| lp64d,rv64*d* | lp64d,rv64g* \
+		| lp64q,rv64*q* )
 			;;
 		*)
 			echo "--with-abi=${with_abi} is not supported for ISA ${with_arch}" 1>&2

gcc/config/riscv/pic.md

@@ -22,13 +22,20 @@
 ;; Simplify PIC loads to static variables.
 ;; These should go away once we figure out how to emit auipc discretely.
 
-(define_insn "*local_pic_load<mode>"
+(define_insn "*local_pic_load_s<mode>"
   [(set (match_operand:ANYI 0 "register_operand" "=r")
-	(mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
+	(sign_extend:ANYI (mem:ANYI (match_operand 1 "absolute_symbolic_operand" ""))))]
   "USE_LOAD_ADDRESS_MACRO (operands[1])"
   "<load>\t%0,%1"
   [(set (attr "length") (const_int 8))])
 
+(define_insn "*local_pic_load_u<mode>"
+  [(set (match_operand:ZERO_EXTEND_LOAD 0 "register_operand" "=r")
+	(zero_extend:ZERO_EXTEND_LOAD (mem:ZERO_EXTEND_LOAD (match_operand 1 "absolute_symbolic_operand" ""))))]
+  "USE_LOAD_ADDRESS_MACRO (operands[1])"
+  "<load>u\t%0,%1"
+  [(set (attr "length") (const_int 8))])
+
 (define_insn "*local_pic_load<mode>"
   [(set (match_operand:ANYF 0 "register_operand" "=f")
 	(mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))

gcc/config/riscv/riscv-c.c

@@ -37,6 +37,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_RVC)
     builtin_define ("__riscv_compressed");
 
+  if (TARGET_RVE)
+    builtin_define ("__riscv_32e");
+
   if (TARGET_ATOMIC)
     builtin_define ("__riscv_atomic");
 
@@ -73,6 +76,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
     case ABI_LP64D:
       builtin_define ("__riscv_float_abi_double");
       break;
+
+    case ABI_LP64Q:
+      builtin_define ("__riscv_float_abi_quad");
+      break;
     }
 
   switch (riscv_cmodel)

gcc/config/riscv/riscv-opts.h

@@ -27,7 +27,8 @@ enum riscv_abi_type {
   ABI_ILP32D,
   ABI_LP64,
   ABI_LP64F,
-  ABI_LP64D
+  ABI_LP64D,
+  ABI_LP64Q
 };
 extern enum riscv_abi_type riscv_abi;
 

gcc/config/riscv/riscv-protos.h

@@ -51,7 +51,7 @@ extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
 extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
 extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
 extern rtx riscv_subword (rtx, bool);
-extern bool riscv_split_64bit_move_p (rtx, rtx);
+extern bool riscv_split_move_p (rtx, rtx);
 extern void riscv_split_doubleword_move (rtx, rtx);
 extern const char *riscv_output_move (rtx, rtx);
 extern const char *riscv_output_gpr_save (unsigned);