Add Tier 3 Thumb-mode targets for Armv7-A, Armv7-R and Armv8-R

compiler/rustc_target/src/spec/mod.rs

@@ -1596,8 +1596,11 @@ supported_targets! {
     ("armebv7r-none-eabi", armebv7r_none_eabi),
     ("armebv7r-none-eabihf", armebv7r_none_eabihf),
     ("armv7r-none-eabi", armv7r_none_eabi),
+    ("thumbv7r-none-eabi", thumbv7r_none_eabi),
     ("armv7r-none-eabihf", armv7r_none_eabihf),
+    ("thumbv7r-none-eabihf", thumbv7r_none_eabihf),
     ("armv8r-none-eabihf", armv8r_none_eabihf),
+    ("thumbv8r-none-eabihf", thumbv8r_none_eabihf),
 
     ("armv7-rtems-eabihf", armv7_rtems_eabihf),
 
@@ -1649,7 +1652,9 @@ supported_targets! {
     ("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf),
 
     ("armv7a-none-eabi", armv7a_none_eabi),
+    ("thumbv7a-none-eabi", thumbv7a_none_eabi),
     ("armv7a-none-eabihf", armv7a_none_eabihf),
+    ("thumbv7a-none-eabihf", thumbv7a_none_eabihf),
     ("armv7a-nuttx-eabi", armv7a_nuttx_eabi),
     ("armv7a-nuttx-eabihf", armv7a_nuttx_eabihf),
     ("armv7a-vex-v5", armv7a_vex_v5),

compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs

@@ -1,40 +1,8 @@
-// Generic ARMv7-A target for bare-metal code - floating point disabled
-//
-// This is basically the `armv7-unknown-linux-gnueabi` target with some changes
-// (listed below) to bring it closer to the bare-metal `thumb` & `aarch64`
-// targets:
-//
-// - `TargetOptions.features`: added `+strict-align`. rationale: unaligned
-// memory access is disabled on boot on these cores
-// - linker changed to LLD. rationale: C is not strictly needed to build
-// bare-metal binaries (the `gcc` linker has the advantage that it knows where C
-// libraries and crt*.o are but it's not much of an advantage here); LLD is also
-// faster
-// - `panic_strategy` set to `abort`. rationale: matches `thumb` targets
-// - `relocation-model` set to `static`; also no PIE, no relro and no dynamic
-// linking. rationale: matches `thumb` targets
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
-    let opts = TargetOptions {
-        abi: Abi::Eabi,
-        llvm_floatabi: Some(FloatAbi::Soft),
-        linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-        linker: Some("rust-lld".into()),
-        features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(),
-        relocation_model: RelocModel::Static,
-        disable_redzone: true,
-        max_atomic_width: Some(64),
-        panic_strategy: PanicStrategy::Abort,
-        emit_debug_gdb_scripts: false,
-        c_enum_min_bits: Some(8),
-        has_thumb_interworking: true,
-        ..Default::default()
-    };
     Target {
         llvm_target: "armv7a-none-eabi".into(),
         metadata: TargetMetadata {
@@ -46,6 +14,13 @@ pub(crate) fn target() -> Target {
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-        options: opts,
+        options: TargetOptions {
+            abi: Abi::Eabi,
+            llvm_floatabi: Some(FloatAbi::Soft),
+            features: "+soft-float,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
     }
 }

compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs

@@ -1,32 +1,8 @@
-// Generic ARMv7-A target for bare-metal code - floating point enabled (assumes
-// FPU is present and emits FPU instructions)
-//
-// This is basically the `armv7-unknown-linux-gnueabihf` target with some
-// changes (list in `armv7a_none_eabi.rs`) to bring it closer to the bare-metal
-// `thumb` & `aarch64` targets.
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
-    let opts = TargetOptions {
-        abi: Abi::EabiHf,
-        llvm_floatabi: Some(FloatAbi::Hard),
-        linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-        linker: Some("rust-lld".into()),
-        features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(),
-        relocation_model: RelocModel::Static,
-        disable_redzone: true,
-        max_atomic_width: Some(64),
-        panic_strategy: PanicStrategy::Abort,
-        emit_debug_gdb_scripts: false,
-        // GCC defaults to 8 for arm-none here.
-        c_enum_min_bits: Some(8),
-        has_thumb_interworking: true,
-        ..Default::default()
-    };
     Target {
         llvm_target: "armv7a-none-eabihf".into(),
         metadata: TargetMetadata {
@@ -38,6 +14,13 @@ pub(crate) fn target() -> Target {
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-        options: opts,
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            features: "+vfp3d16,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
     }
 }

compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs

@@ -1,36 +1,25 @@
 // Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
         llvm_target: "armv7r-none-eabi".into(),
         metadata: TargetMetadata {
-            description: Some("Armv7-R".into()),
+            description: Some("Bare Armv7-R".into()),
             tier: Some(2),
             host_tools: Some(false),
             std: Some(false),
         },
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-
         options: TargetOptions {
             abi: Abi::Eabi,
             llvm_floatabi: Some(FloatAbi::Soft),
-            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-            linker: Some("rust-lld".into()),
-            relocation_model: RelocModel::Static,
-            panic_strategy: PanicStrategy::Abort,
             max_atomic_width: Some(64),
-            emit_debug_gdb_scripts: false,
-            // GCC defaults to 8 for arm-none here.
-            c_enum_min_bits: Some(8),
             has_thumb_interworking: true,
-            ..Default::default()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs

@@ -1,37 +1,26 @@
 // Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
         llvm_target: "armv7r-none-eabihf".into(),
         metadata: TargetMetadata {
-            description: Some("Armv7-R, hardfloat".into()),
+            description: Some("Bare Armv7-R, hardfloat".into()),
             tier: Some(2),
             host_tools: Some(false),
             std: Some(false),
         },
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-
         options: TargetOptions {
             abi: Abi::EabiHf,
             llvm_floatabi: Some(FloatAbi::Hard),
-            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-            linker: Some("rust-lld".into()),
-            relocation_model: RelocModel::Static,
-            panic_strategy: PanicStrategy::Abort,
             features: "+vfp3d16".into(),
             max_atomic_width: Some(64),
-            emit_debug_gdb_scripts: false,
-            // GCC defaults to 8 for arm-none here.
-            c_enum_min_bits: Some(8),
             has_thumb_interworking: true,
-            ..Default::default()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs

@@ -1,9 +1,6 @@
 // Targets the Little-endian Cortex-R52 processor (ARMv8-R)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -21,10 +18,6 @@ pub(crate) fn target() -> Target {
         options: TargetOptions {
             abi: Abi::EabiHf,
             llvm_floatabi: Some(FloatAbi::Hard),
-            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-            linker: Some("rust-lld".into()),
-            relocation_model: RelocModel::Static,
-            panic_strategy: PanicStrategy::Abort,
             // Armv8-R requires a minimum set of floating-point features equivalent to:
             // fp-armv8, SP-only, with 16 DP (32 SP) registers
             // LLVM defines Armv8-R to include these features automatically.
@@ -36,11 +29,8 @@ pub(crate) fn target() -> Target {
             // Arm Cortex-R52 Processor Technical Reference Manual
             // - Chapter 15 Advanced SIMD and floating-point support
             max_atomic_width: Some(64),
-            emit_debug_gdb_scripts: false,
-            // GCC defaults to 8 for arm-none here.
-            c_enum_min_bits: Some(8),
             has_thumb_interworking: true,
-            ..Default::default()
+            ..base::arm_none::opts()
         },
     }
 }

compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs

@@ -0,0 +1,26 @@
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7a-none-eabi".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-A".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::Eabi,
+            llvm_floatabi: Some(FloatAbi::Soft),
+            features: "+soft-float,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}

compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs

@@ -0,0 +1,26 @@
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7a-none-eabihf".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-A, hardfloat".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            features: "+vfp3d16,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}

compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs

@@ -0,0 +1,25 @@
+// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7r-none-eabi".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-R".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::Eabi,
+            llvm_floatabi: Some(FloatAbi::Soft),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}

compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs

@@ -0,0 +1,26 @@
+// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7r-none-eabihf".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-R, hardfloat".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            features: "+vfp3d16".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}

compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs

@@ -0,0 +1,36 @@
+// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv8r-none-eabihf".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv8-R, hardfloat".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            // Armv8-R requires a minimum set of floating-point features equivalent to:
+            // fp-armv8, SP-only, with 16 DP (32 SP) registers
+            // LLVM defines Armv8-R to include these features automatically.
+            //
+            // The Cortex-R52 supports these default features and optionally includes:
+            // neon-fp-armv8, SP+DP, with 32 DP registers
+            //
+            // Reference:
+            // Arm Cortex-R52 Processor Technical Reference Manual
+            // - Chapter 15 Advanced SIMD and floating-point support
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}