Add `f16` inline ASM support for `nvptx64-nvidia-cuda` by beetrees · Pull Request #161667 · rust-lang/rust

beetrees · 2026-08-24T12:13:27Z

This PR adds f16 inline ASM support for nvptx64-nvidia-cuda.

Ping target maintainers: @kjetilkjeka @kulst

Tracking issues:
f16 inline ASM: #125398 (part of #116909)
PTX inline ASM: #93335

rustbot · 2026-08-24T12:13:33Z

rustbot has assigned @davidtwco.
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folkertdev · 2026-09-03T21:21:21Z

Can we get an actual "LGTM" from a target maintainer here?

folkertdev · 2026-09-17T17:53:11Z

@kjetilkjeka @kulst can you let us know that this looks good to you?

kulst · 2026-09-18T14:06:17Z

Thank you for the contribution and sorry for the delay!

PTX allows to hold narrower types in wider registers and to my knowledge floating point types are no exception to this.

So apart from the mov type nits, the PR LGTM.

folkertdev · 2026-09-18T14:13:20Z

So apart from the mov type nits, the PR LGTM.

did you forget to post something? what is this referring to?

kulst

Not in particular a problem of this PR since the test was wrong before, but could you replace i16, i32, i64 in the mov instructions with b16, b32 and b64?

i16, i32, i64 are not valid PTX types.

Full Diff

diff --git a/tests/assembly-llvm/asm/nvptx-types.rs b/tests/assembly-llvm/asm/nvptx-types.rs
index d4f34dd7733..15c4dabbfec 100644
--- a/tests/assembly-llvm/asm/nvptx-types.rs
+++ b/tests/assembly-llvm/asm/nvptx-types.rs
@@ -38,96 +38,96 @@ pub unsafe fn $func(x: $ty) -> $ty {
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg16_i8
 // CHECK: // begin inline asm
-// CHECK: mov.i16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg16_i8 i8 reg16 "mov.i16");
+check!(reg16_i8 i8 reg16 "mov.b16");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg16_i16
 // CHECK: // begin inline asm
-// CHECK: mov.i16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg16_i16 i16 reg16 "mov.i16");
+check!(reg16_i16 i16 reg16 "mov.b16");
 
 // CHECK-LABEL: .visible .func (.param .align 2 .b8 func_retval0[2]) reg16_f16
 // CHECK: // begin inline asm
-// CHECK: mov.i16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b16 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg16_f16 f16 reg16 "mov.i16");
+check!(reg16_f16 f16 reg16 "mov.b16");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_i8
 // CHECK: // begin inline asm
-// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg32_i8 i8 reg32 "mov.i32");
+check!(reg32_i8 i8 reg32 "mov.b32");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_i16
 // CHECK: // begin inline asm
-// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg32_i16 i16 reg32 "mov.i32");
+check!(reg32_i16 i16 reg32 "mov.b32");
 
 // CHECK-LABEL: .visible .func (.param .align 2 .b8 func_retval0[2]) reg32_f16
 // CHECK: // begin inline asm
-// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg32_f16 f16 reg32 "mov.i32");
+check!(reg32_f16 f16 reg32 "mov.b32");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_i32
 // CHECK: // begin inline asm
-// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg32_i32 i32 reg32 "mov.i32");
+check!(reg32_i32 i32 reg32 "mov.b32");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg32_f32
 // CHECK: // begin inline asm
-// CHECK: mov.i32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b32 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg32_f32 f32 reg32 "mov.i32");
+check!(reg32_f32 f32 reg32 "mov.b32");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_i8
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_i8 i8 reg64 "mov.i64");
+check!(reg64_i8 i8 reg64 "mov.b64");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_i16
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_i16 i16 reg64 "mov.i64");
+check!(reg64_i16 i16 reg64 "mov.b64");
 
 // CHECK-LABEL: .visible .func (.param .align 2 .b8 func_retval0[2]) reg64_f16
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_f16 f16 reg64 "mov.i64");
+check!(reg64_f16 f16 reg64 "mov.b64");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_i32
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_i32 i32 reg64 "mov.i64");
+check!(reg64_i32 i32 reg64 "mov.b64");
 
 // CHECK-LABEL: .visible .func (.param .b32 func_retval0) reg64_f32
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_f32 f32 reg64 "mov.i64");
+check!(reg64_f32 f32 reg64 "mov.b64");
 
 // CHECK-LABEL: .visible .func (.param .b64 func_retval0) reg64_i64
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_i64 i64 reg64 "mov.i64");
+check!(reg64_i64 i64 reg64 "mov.b64");
 
 // CHECK-LABEL: .visible .func (.param .b64 func_retval0) reg64_f64
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_f64 f64 reg64 "mov.i64");
+check!(reg64_f64 f64 reg64 "mov.b64");
 
 // CHECK-LABEL: .visible .func (.param .b64 func_retval0) reg64_ptr
 // CHECK: // begin inline asm
-// CHECK: mov.i64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
+// CHECK: mov.b64 %{{[a-z0-9]+}}, %{{[a-z0-9]+}};
 // CHECK: // end inline asm
-check!(reg64_ptr ptr reg64 "mov.i64");
+check!(reg64_ptr ptr reg64 "mov.b64");

View changes since this review

rustbot · 2026-09-22T13:37:26Z

This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

folkertdev

Thanks all!

r? me

@bors r+ rollup

View changes since this review

rust-bors · 2026-09-22T16:40:50Z

📌 Commit baf4778 has been approved by folkertdev

It is now in the queue for this repository.

@kjetilkjeka

…olkertdev Add `f16` inline ASM support for `nvptx64-nvidia-cuda` This PR adds `f16` inline ASM support for `nvptx64-nvidia-cuda`. Ping target maintainers: @kjetilkjeka @kulst Tracking issues: `f16` inline ASM: rust-lang#125398 (part of rust-lang#116909) PTX inline ASM: rust-lang#93335

…uwer Rollup of 13 pull requests Successful merges: - #156949 (Detect missing else in let statement) - #160436 (stabilize `Box::take`) - #160570 (macro_metavar_expr_concat: support concatenating into string literals) - #162837 (Dedicated Display type for CStr::display) - #163099 (Use wrapping arithmetic in `from_str_radix`) - #163166 (Tiny cleanups to deferred liveness) - #161667 (Add `f16` inline ASM support for `nvptx64-nvidia-cuda`) - #163063 (Restore `Send` and `Sync` for `BorrowedCursor`) - #163097 (OpenBSD/sparc64 has switched from GCC to Clang) - #163126 (Skip redundant storage-conflict updates during coroutine layout) - #163135 (librustdoc: remove stale dep on base64) - #163146 (tests: Update `f16b` codegen test for LoongArch and RISC-V) - #163159 (treat inductive cycles as ambig)

@kjetilkjeka

Rollup merge of #161667 - beetrees:f16-inline-asm-nvptx, r=folkertdev Add `f16` inline ASM support for `nvptx64-nvidia-cuda` This PR adds `f16` inline ASM support for `nvptx64-nvidia-cuda`. Ping target maintainers: @kjetilkjeka @kulst Tracking issues: `f16` inline ASM: #125398 (part of #116909) PTX inline ASM: #93335

rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Aug 24, 2026

rustbot assigned davidtwco Aug 24, 2026

beetrees mentioned this pull request Aug 24, 2026

Enable f16 and f128 in assembly on platforms that support it #125398

Open

folkertdev added the F-f16_and_f128 `#![feature(f16)]`, `#![feature(f128)]` label Aug 24, 2026

folkertdev mentioned this pull request Aug 28, 2026

Stabilizing f16 rust-lang/goals#655

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kulst suggested changes Sep 18, 2026

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Comment thread tests/assembly-llvm/asm/nvptx-types.rs Outdated

beetrees force-pushed the f16-inline-asm-nvptx branch from cd5953d to 119eacb Compare September 22, 2026 13:24

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beetrees force-pushed the f16-inline-asm-nvptx branch from 119eacb to f0286d1 Compare September 22, 2026 13:37

Add f16 inline ASM support for nvptx64-nvidia-cuda

baf4778

beetrees force-pushed the f16-inline-asm-nvptx branch from f0286d1 to baf4778 Compare September 22, 2026 13:41

folkertdev approved these changes Sep 22, 2026

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rustbot assigned folkertdev Sep 22, 2026

rust-bors Bot added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Sep 22, 2026

rustbot unassigned davidtwco Sep 22, 2026

This was referenced Sep 22, 2026

Rollup of 15 pull requests #163175

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Rollup of 13 pull requests #163178

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rust-bors Bot merged commit c81d09c into rust-lang:main Sep 23, 2026
13 checks passed

rustbot added this to the 1.100.0 milestone Sep 23, 2026

beetrees deleted the f16-inline-asm-nvptx branch September 23, 2026 10:20

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Add `f16` inline ASM support for `nvptx64-nvidia-cuda` - #161667

Add `f16` inline ASM support for `nvptx64-nvidia-cuda`#161667
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