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Fix flash latency for F4x5RG running full speed at 168MHz #1174

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Merged
merged 1 commit into from
Sep 15, 2020
Merged

Fix flash latency for F4x5RG running full speed at 168MHz #1174

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4 changes: 2 additions & 2 deletions variants/Generic_F4x5RG/variant.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -158,7 +158,7 @@ static uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
return 0; // FAIL
}

Expand Down Expand Up @@ -208,7 +208,7 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
return 0; // FAIL
}

Expand Down