[m(x)isa] add A & Zalrsc

stnolting · Feb 8, 2025 · 92f3b8b · 92f3b8b
1 parent 4941e07
commit 92f3b8b
Show file tree

Hide file tree

Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc
@@ -221,6 +221,7 @@ will _not_ cause an illegal instruction exception.
 [options="header",grid="rows"]
 |=======================
 | Bit   | Name [C] | R/W | Function
+| 0     | `CSR_MISA_A_EXT` | r/- | **A**: CPU extension (atomic memory access) available, set when <<_a_isa_extension>> enabled
 | 1     | `CSR_MISA_B_EXT` | r/- | **B**: CPU extension (bit-manipulation) available, set when <<_b_isa_extension>> enabled
 | 2     | `CSR_MISA_C_EXT` | r/- | **C**: CPU extension (compressed instruction) available, set when <<_c_isa_extension>> enabled
 | 4     | `CSR_MISA_E_EXT` | r/- | **E**: CPU extension (embedded) available, set when <<_e_isa_extension>> enabled
@@ -1022,7 +1023,7 @@ discover additional ISA (sub-)extensions and CPU configuration options.
 | 23    | `CSR_MXISA_ZBB`       | r/- | <<_zbb_isa_extension>> available
 | 24    | `CSR_MXISA_ZBS`       | r/- | <<_zbs_isa_extension>> available
 | 25    | `CSR_MXISA_ZAAMO`     | r/- | <<_zaamo_isa_extension>> available
-| 28:26 | -                     | r/- | _reserved_, hardwired to zero
+| 26    | `CSR_MXISA_ZALRSC`    | r/- | <<_zalrsc_isa_extension>> available
 | 27    | `CSR_MXISA_CLKGATE`   | r/- | sleep-mode clock gating implemented when set (`CPU_CLOCK_GATING_EN`), see <<_cpu_tuning_options>>
 | 28    | `CSR_MXISA_RFHWRST`   | r/- | full hardware reset of register file available when set (`CPU_RF_HW_RST_EN`), see <<_cpu_tuning_options>>
 | 29    | `CSR_MXISA_FASTMUL`   | r/- | fast multiplication available when set (`CPU_FAST_MUL_EN`), see <<_cpu_tuning_options>>

diff --git a/sw/lib/include/neorv32_cpu_csr.h b/sw/lib/include/neorv32_cpu_csr.h
@@ -9,8 +9,6 @@
 /**
  * @file neorv32_cpu_csr.h
  * @brief Control and Status Registers (CSR) definitions.
- *
- * @see https://stnolting.github.io/neorv32/sw/files.html
  */
 
 #ifndef neorv32_cpu_csr_h
@@ -291,6 +289,7 @@ enum NEORV32_CSR_MIP_enum {
  * CPU misa CSR (r/-): Machine instruction set extensions
  **************************************************************************/
 enum NEORV32_CSR_MISA_enum {
+  CSR_MISA_A      =  0, /**< CPU misa CSR  (0): A: Atomic memory accesses CPU extension available (r/-)*/
   CSR_MISA_B      =  1, /**< CPU misa CSR  (1): B: Bit manipulation CPU extension available (r/-)*/
   CSR_MISA_C      =  2, /**< CPU misa CSR  (2): C: Compressed instructions CPU extension available (r/-)*/
   CSR_MISA_E      =  4, /**< CPU misa CSR  (4): E: Embedded CPU extension available (r/-) */
@@ -333,7 +332,8 @@ enum NEORV32_CSR_MXISA_enum {
   CSR_MXISA_ZBA       = 22, /**< CPU mxisa CSR (22): shifted-add bit-manipulation operations (r/-)*/
   CSR_MXISA_ZBB       = 23, /**< CPU mxisa CSR (23): basic bit-manipulation operations (r/-)*/
   CSR_MXISA_ZBS       = 24, /**< CPU mxisa CSR (24): single-bit bit-manipulation operations (r/-)*/
-  CSR_MXISA_ZAAMO     = 25, /**< CPU mxisa CSR (25): atomic memory operations (r/-)*/
+  CSR_MXISA_ZAAMO     = 25, /**< CPU mxisa CSR (25): atomic read-modify-write operations (r/-)*/
+  CSR_MXISA_ZALRSC    = 26, /**< CPU mxisa CSR (26): atomic reservation-set operations (r/-)*/
   // Tuning options
   CSR_MXISA_CLKGATE   = 27, /**< CPU mxisa CSR (27): clock gating enabled (r/-)*/
   CSR_MXISA_RFHWRST   = 28, /**< CPU mxisa CSR (28): register file has full hardware reset (r/-)*/