⚠️ remove execute in-place (XIP) module

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 01.02.2025 | 1.11.0.6 | :warning: remove XIP module | [#1175](https://github.com/stnolting/neorv32/pull/1175) |
 | 01.02.2025 | 1.11.0.5 | minor rtl optimizations and cleanups; :warning: remove DMA "fence" feature | [#1174](https://github.com/stnolting/neorv32/pull/1174) |
 | 28.01.2025 | 1.11.0.4 | :bug: fix crt0's entry address being overridden by core0's constructors (that do not backup any registers) | [#1172](https://github.com/stnolting/neorv32/pull/1172) |
 | 28.01.2025 | 1.11.0.3 | :bug: fix BOOTROM addressing (index was out-of-range) | [#1171](https://github.com/stnolting/neorv32/pull/1171) |

README.md

@@ -182,7 +182,6 @@ allows booting application code via UART, TWI or from external SPI flash
 
 * true-random number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng)) based
 on the [neoTRNG](https://github.com/stnolting/neoTRNG)
-* execute-in-place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to execute code right out of a SPI flash
 * custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
 for custom tightly-coupled co-processors, accelerators or interfaces
 * direct memory access controller ([DMA](https://stnolting.github.io/neorv32/#_direct_memory_access_controller_dma)) for CPU-independent

docs/datasheet/on_chip_debugger.adoc

@@ -762,9 +762,8 @@ return to the address stored in `dpc` by automatically moving `dpc` to the progr
 
 "Normal" software breakpoints (using GDB's `b`/`break` command) are implemented by temporarily replacing the according
 instruction word by an `[c.]ebreak` instruction. However, this is not possible when debugging code that is executed from
-read-only memory (for example when debugging programs that are executed via the <<_execute_in_place_module_xip>>).
-To circumvent this limitation a hardware trigger logic allows to (re-)enter debug-mode when instruction execution
-reaches a programmable address. These "hardware-assisted breakpoints" are used by GDB's `hb`/`hbreak` commands.
+read-only memory. To circumvent this limitation a hardware trigger logic allows to (re-)enter debug-mode when instruction
+execution reaches a programmable address. These "hardware-assisted breakpoints" are used by GDB's `hb`/`hbreak` commands.
 
 The RISC-V `Sdtrig` ISA extension adds a programmable _trigger module_ to the CPU core that is enabled via the
 <<_sdtrig_isa_extension>> generic. The trigger module implements a subset of the features described in the

docs/datasheet/overview.adoc

@@ -76,7 +76,6 @@ include::rationale.adoc[]
 * optional general purpose IO and PWM; a native NeoPixel(c)-compatible smart LED interface
 * optional embedded memories and caches for data, instructions and bootloader
 * optional external memory interface for custom connectivity
-* optional execute in-place (XIP) module to execute code directly form an external SPI flash
 * optional DMA controller for CPU-independent data transfers
 * optional CRC module to check data integrity
 * on-chip debugger compatible with OpenOCD and GDB including hardware trigger module and optional authentication
@@ -215,8 +214,7 @@ rtl/core
 ├-neorv32_twi.vhd               - Two wire serial interface controller
 ├-neorv32_uart.vhd              - Universal async. receiver/transmitter
 ├-neorv32_wdt.vhd               - Watchdog timer
-├-neorv32_xbus.vhd              - External (Wishbone) bus interface gateways
-└-neorv32_xip.vhd               - Execute in place module
+└-neorv32_xbus.vhd              - External (Wishbone) bus interface gateways
 ...................................
 
 .Replacing Modules for Customization or Optimization

docs/datasheet/soc.adoc

@@ -22,7 +22,7 @@ image::neorv32_processor.png[align=center]
 * _optional_ SMP <<_dual_core_configuration>>
 * _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>)
 * _optional_ caches (<<_processor_internal_instruction_cache_icache,**I-CACHE**>>, <<_processor_internal_data_cache_dcache,**D-CACHE**>>,
-<<_execute_in_place_module_xip,**XIP-CACHE**>>, <<_processor_external_bus_interface_xbus,**XBUS-CACHE**>>)
+<<_processor_external_bus_interface_xbus,**XBUS-CACHE**>>)
 * _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
 * _optional_ RISC-V-compatible core local interruptor (<<_core_local_interruptor_clint,**CLINT**>>)
 * _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>,
@@ -39,7 +39,6 @@ image::neorv32_processor.png[align=center]
 * _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
 * _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
 * _optional_ general purpose 32-bit timer (<<_general_purpose_timer_gptmr,**GPTMR**>>)
-* _optional_ execute in-place module (<<_execute_in_place_module_xip,**XIP**>>)
 * _optional_ 1-wire serial interface controller (<<_one_wire_serial_interface_controller_onewire,**ONEWIRE**>>), compatible to the 1-wire standard
 * _optional_ autonomous direct memory access controller (<<_direct_memory_access_controller_dma,**DMA**>>)
 * _optional_ stream link interface (<<_stream_link_interface_slink,**SLINK**>>), AXI4-Stream compatible
@@ -116,11 +115,6 @@ to all inputs and output so the synthesis tool can insert an explicit IO (bounda
 | `slink_tx_val_o` |  1 | out |   -   | TX data valid
 | `slink_tx_lst_o` |  1 | out |   -   | TX last element of stream
 | `slink_tx_rdy_i` |  1 |  in | `'L'` | TX allowed to send
-5+^| **<<_execute_in_place_module_xip>>**
-| `xip_csn_o`      |  1 | out |   -   | chip select, low-active
-| `xip_clk_o`      |  1 | out |   -   | serial clock
-| `xip_dat_i`      |  1 |  in | `'L'` | serial data input
-| `xip_dat_o`      |  1 | out |   -   | serial data output
 5+^| **<<_general_purpose_input_and_output_port_gpio>>**
 | `gpio_o`         | 32 | out |   -   | general purpose parallel output
 | `gpio_i`         | 32 |  in | `'L'` | general purpose parallel input (interrupt-capable)
@@ -276,11 +270,6 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 | `XBUS_CACHE_EN`         | boolean   | false         | Implement the external bus cache.
 | `XBUS_CACHE_NUM_BLOCKS` | natural   | 64            | Number of blocks ("lines"). Has to be a power of two.
 | `XBUS_CACHE_BLOCK_SIZE` | natural   | 32            | Size in bytes of each block. Has to be a power of two.
-4+^| **<<_execute_in_place_module_xip>>**
-| `XIP_EN`                | boolean   | false         | Implement the execute in-place module.
-| `XIP_CACHE_EN`          | boolean   | false         | Implement XIP cache.
-| `XIP_CACHE_NUM_BLOCKS`  | natural   | 8             | Number of blocks in XIP cache. Has to be a power of two.
-| `XIP_CACHE_BLOCK_SIZE`  | natural   | 256           | Number of bytes per XIP cache block. Has to be a power of two, min 4.
 4+^| **Peripheral/IO Modules**
 | `IO_DISABLE_SYSINFO`    | boolean   | false         | Disable <<_system_configuration_information_memory_sysinfo>> module; ⚠️ not recommended - for advanced users only!
 | `IO_GPIO_NUM`           | natural   | 0             | Number of general purpose input/output pairs of the <<_general_purpose_input_and_output_port_gpio>>, max 32.
@@ -466,7 +455,7 @@ table (the channel number also corresponds to the according FIRQ priority: 0 = h
 === Address Space
 
 As a 32-bit architecture the NEORV32 can access a 4GB physical address space. By default, this address space is
-split into four main regions. All accesses to "unmapped" addresses (a.k.a. "the void") are redirected to the
+split into three main regions. All accesses to "unmapped" addresses (a.k.a. "the void") are redirected to the
 <<_processor_external_bus_interface_xbus>>. For example, if the internal IMEM is disabled, the accesses to the
 _entire_ address space between `0x00000000` and `0x7FFFFFFF` are converted into XBUS requests. If the XBUS interface
 is not enabled any access to the void will raise a bus error exception.
@@ -489,8 +478,7 @@ can be used to further constrain the physical memory attributes.
 | # | Region                      | PMAs      | Description
 | 1 | Internal IMEM address space | `rwxac`   | For instructions / code and constants; mapped to the internal <<_instruction_memory_imem>> if implemented.
 | 2 | Internal DMEM address space | `rwxac`   | For application runtime data (heap, stack, etc.); mapped to the internal <<_data_memory_dmem>>) if implemented.
-| 3 | Memory-mapped XIP flash     | `r-xac`   | Transparent memory-mapped access to an external <<_execute_in_place_module_xip>> SPI flash.
-| 4 | IO/peripheral address space | `rwxa-`   | Processor-internal peripherals / IO devices including the <<_bootloader_rom_bootrom>>.
+| 3 | IO/peripheral address space | `rwxa-`   | Processor-internal peripherals / IO devices including the <<_bootloader_rom_bootrom>>.
 | - | The "**void**"              | `rwxa[c]` | Unmapped address space. All accesses to this region(s) are redirected to the <<_processor_external_bus_interface_xbus>> if implemented.
 |=======================
 
@@ -538,8 +526,6 @@ customizable memory map implemented via VHDL constants in the main package file
 -- Main Address Regions ---
 constant mem_imem_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- IMEM size via generic
 constant mem_dmem_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- DMEM size via generic
-constant mem_xip_base_c  : std_ulogic_vector(31 downto 0) := x"e0000000"; -- page (4 MSBs) only!
-constant mem_xip_size_c  : natural := 256*1024*1024;
 constant mem_io_base_c   : std_ulogic_vector(31 downto 0) := x"ffe00000";
 constant mem_io_size_c   : natural := 32*64*1024; -- = 32 * iodev_size_c
 ----
@@ -561,10 +547,6 @@ and no `err` signal) will time out raising a bus access fault exception. For exa
 "address space holes" - addresses that are not mapped to any physical module. The resulting exception type corresponds
 to the according access type, i.e. instruction fetch access exception, load access exception or store access exception.
 
-.XIP Timeout
-[NOTE]
-Accesses to the memory-mapped XIP flash (via the <<_execute_in_place_module_xip>>) will _never_ time out.
-
 .External Bus Interface Timeout
 [NOTE]
 Accesses that are delegated to the external bus interface have a different maximum timeout value that is defined by an
@@ -630,14 +612,13 @@ cannot be interrupted. Hence, they execute in an atomic way.
 :sectnums:
 ==== Cache Coherency
 
-In total the NEORV32 Processor provides up to four optional caches organized in two levels. Level-1
+In total the NEORV32 Processor provides up to three optional caches organized in two levels. Level-1
 caches are closer to the CPU while level-2 caches are closer to main memory (however, this highly depends
 on the the actual cache configurations).
 
 * The <<_processor_internal_data_cache_dcache>> (level-1)
 * The <<_processor_internal_instruction_cache_icache>> (level-1)
 * The cache of the <<_processor_external_bus_interface_xbus>> (level-2)
-* The cache of the <<_execute_in_place_module_xip>> (level-2)
 
 As all caches operate transparently for the software, special attention must therefore be paid to coherence.
 Note that coherence and cache _synchronization_ is **not** performed by the hardware itself (there is no
@@ -822,6 +803,4 @@ include::soc_neoled.adoc[]
 
 include::soc_gptmr.adoc[]
 
-include::soc_xip.adoc[]
-
 include::soc_sysinfo.adoc[]

docs/datasheet/soc_sysinfo.adoc

@@ -81,8 +81,8 @@ Bit fields in this register are set to all-zero if the according memory system i
 | `6`     | `SYSINFO_SOC_DCACHE`       | set if processor-internal data cache is implemented (via top's `DCACHE_EN` generic)
 | `7`     | -                          |_reserved_, read as zero
 | `8`     | `SYSINFO_SOC_XBUS_CACHE`   | set if external bus interface cache is implemented (via top's `XBUS_CACHE_EN` generic)
-| `9`     | `SYSINFO_SOC_XIP`          | set if XIP module is implemented (via top's `XIP_EN` generic)
-| `10`    | `SYSINFO_SOC_XIP_CACHE`    | set if XIP cache is implemented (via top's `XIP_CACHE_EN` generic)
+| `9`     | -                          |_reserved_, read as zero
+| `10`    | -                          |_reserved_, read as zero
 | `11`    | `SYSINFO_SOC_OCD_AUTH`     | set if on-chip debugger authentication is implemented (via top's `OCD_AUTHENTICATION` generic)
 | `12`    | `SYSINFO_SOC_IMEM_ROM`     | set if processor-internal IMEM is implemented as pre-initialized ROM (via top's `BOOT_MODE_SELECT` generic; see <<_boot_configuration>>)
 | `13`    | `SYSINFO_SOC_IO_TWD`       | set if TWD is implemented (via top's `IO_TWD_EN` generic)
@@ -113,7 +113,6 @@ The SYSINFO cache register provides information about the configuration of the p
 
 * <<_processor_internal_instruction_cache_icache>>
 * <<_processor_internal_data_cache_dcache>>
-* <<_execute_in_place_module_xip>> cache (XIP-CACHE)
 * <<_processor_external_bus_interface_xbus>> cache (XBUS-CACHE)
 
 .SYSINFO `CACHE` Bits
@@ -125,8 +124,8 @@ The SYSINFO cache register provides information about the configuration of the p
 | `7:4`   | `SYSINFO_CACHE_INST_NUM_BLOCKS_3 : SYSINFO_CACHE_INST_NUM_BLOCKS_0` | _log2_(i-cache number of cache blocks), via top's `ICACHE_NUM_BLOCKS` generic
 | `11:8`  | `SYSINFO_CACHE_DATA_BLOCK_SIZE_3 : SYSINFO_CACHE_DATA_BLOCK_SIZE_0` | _log2_(d-cache block size in bytes), via top's `DCACHE_BLOCK_SIZE` generic
 | `15:12` | `SYSINFO_CACHE_DATA_NUM_BLOCKS_3 : SYSINFO_CACHE_DATA_NUM_BLOCKS_0` | _log2_(d-cache number of cache blocks), via top's `DCACHE_NUM_BLOCKS` generic
-| `19:16` | `SYSINFO_CACHE_XIP_BLOCK_SIZE_3 : SYSINFO_CACHE_XIP_BLOCK_SIZE_0`   | _log2_(xip-cache block size in bytes), via top's `XIP_CACHE_BLOCK_SIZE` generic
-| `23:20` | `SYSINFO_CACHE_XIP_NUM_BLOCKS_3 : SYSINFO_CACHE_XIP_NUM_BLOCKS_0`   | _log2_(xip-cache number of cache blocks), via top's `XIP_CACHE_NUM_BLOCKS` generic
+| `19:16` | `0000`                                                              | _reserved_
+| `23:20` | `0000`                                                              | _reserved_
 | `27:24` | `SYSINFO_CACHE_XBUS_BLOCK_SIZE_3 : SYSINFO_CACHE_XBUS_BLOCK_SIZE_0` | _log2_(xbus-cache block size in bytes), via top's `XBUS_CACHE_BLOCK_SIZE` generic
 | `31:28` | `SYSINFO_CACHE_XBUS_NUM_BLOCKS_3 : SYSINFO_CACHE_XBUS_NUM_BLOCKS_0` | _log2_(xbus-cache number of cache blocks), via top's `XBUS_CACHE_NUM_BLOCKS` generic
 |=======================