A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
Pipline MIPS processor implementation on Basys 3 with hazard handling and memory mapped IO.
The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.
ECE552: Computer Architecture — Fall 2020.
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