A FPGA implementation of the NTP and NTS protocols
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Updated
May 31, 2023 - Verilog
A FPGA implementation of the NTP and NTS protocols
Ring oscillator core written in Verilog. Forked from https://git.cryptech.is/rng/rosc_entropy.git/
Key memory core written in Verilog. Used by the FPGA_NTP_SERVER project
SHA1 core written in Verilog. Forked from https://git.cryptech.is/hash/sha1.git/
NTS core written in Verilog. This is just a core, see the FPGA_NTP_SERVER project for a complete implementation of the NTS protocol in a FPGA.
api_extension core written in Verilog. Used by the FPGA_NTP_SERVER project
AES core written in Verilog. Forked from https://git.cryptech.is/cipher/aes.git/
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