Using-Verilog-and-ModelSim-simulator-to-design-a-Pipelined-MIPS-Lite-CPU

Using-Verilog-and-ModelSim-simulator to design-a-Pipelined-MIPS-Lite-CPU

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU.v		ALU.v
ALU1bit.v		ALU1bit.v
BranchADD.v		BranchADD.v
CPU.v		CPU.v
CompilerB.v		CompilerB.v
CompilerBEQ.v		CompilerBEQ.v
EX.v		EX.v
FullAdder.v		FullAdder.v
HiLo.v		HiLo.v
ID.v		ID.v
Jump.v		Jump.v
MUX.v		MUX.v
MUX2to1.v		MUX2to1.v
MUX2to1_5bit.v		MUX2to1_5bit.v
Multiplier.v		Multiplier.v
PC.v		PC.v
PCADDFOUR.v		PCADDFOUR.v
README.md		README.md
Shifter.v		Shifter.v
alu_ctl.v		alu_ctl.v
control_single.v		control_single.v
instruction_mem.v		instruction_mem.v
memory.v		memory.v
mips_processor.v		mips_processor.v
mips_single.v		mips_single.v
reg32.v		reg32.v
reg_EX_MEM.v		reg_EX_MEM.v
reg_ID_EX.v		reg_ID_EX.v
reg_IF_ID.v		reg_IF_ID.v
reg_file.v		reg_file.v
sign extend.v		sign extend.v
stage_IF.v		stage_IF.v
stage_MEM.v		stage_MEM.v
stage_WB.v		stage_WB.v
tb_Alu.v		tb_Alu.v
tb_BranchADD.v		tb_BranchADD.v
tb_CPU.v		tb_CPU.v
tb_CompilerB.v		tb_CompilerB.v
tb_Jump.v		tb_Jump.v
tb_PC.v		tb_PC.v

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