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Fix link error and clang warnings #35

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Fix link error and clang warnings #35

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cf5f8ce
add override keyword
Aug 2, 2016
e8355fe
remove copy-and-paste typo.
Aug 2, 2016
1e35916
RISCVAsmPrinter requires InstPrinter to link
Aug 2, 2016
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2 changes: 1 addition & 1 deletion lib/Target/RISCV/LLVMBuild.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -30,5 +30,5 @@ has_jit = 1
type = Library
name = RISCVCodeGen
parent = RISCV
required_libraries = AsmPrinter CodeGen Core MC SelectionDAG RISCVDesc RISCVInfo Support Target
required_libraries = AsmPrinter CodeGen Core MC SelectionDAG RISCVAsmPrinter RISCVDesc RISCVInfo Support Target
add_to_library_groups = RISCV
10 changes: 5 additions & 5 deletions lib/Target/RISCV/RISCVFrameLowering.h
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Expand Up @@ -20,12 +20,12 @@ class RISCVFrameLowering : public TargetFrameLowering {
public:
RISCVFrameLowering();

bool hasFP(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const override;

/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction&, MachineBasicBlock&) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
void emitPrologue(MachineFunction&, MachineBasicBlock&) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;

MachineBasicBlock::iterator
eliminateCallFramePseudoInstr(MachineFunction &MF,
Expand All @@ -35,9 +35,9 @@ class RISCVFrameLowering : public TargetFrameLowering {
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;

bool hasReservedCallFrame(const MachineFunction &MF) const;
bool hasReservedCallFrame(const MachineFunction &MF) const override;

void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS) const override;
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2 changes: 1 addition & 1 deletion lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Expand Up @@ -213,7 +213,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
}

// Override SelectionDAGISel.
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
void Select(SDNode *Node) override;
virtual void processFunctionAfterISel(MachineFunction &MF);
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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4 changes: 2 additions & 2 deletions lib/Target/RISCV/RISCVISelLowering.h
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Expand Up @@ -120,7 +120,7 @@ class RISCVTargetLowering : public TargetLowering {
unsigned
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
const char *getTargetNodeName(unsigned Opcode) const override;
std::pair<unsigned, const TargetRegisterClass *>
Expand Down Expand Up @@ -153,7 +153,7 @@ class RISCVTargetLowering : public TargetLowering {
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const;
LLVMContext &Context) const override;

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
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2 changes: 0 additions & 2 deletions lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -217,8 +217,6 @@ unsigned
RISCVInstrInfo::InsertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I, int64_t offset,
ArrayRef<MachineOperand> Cond,
const DebugLoc &DL) const {
// Shouldn't be a fall through.
assert(&MBB && "InsertBranch must not be told to insert a fallthrough");
assert(Cond.size() <= 4 &&
"RISCV branch conditions have less than four components!");

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