HPS_CONTROL_FPGA_LED.map.smsg

Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_1_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_001.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_1_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router_001.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_1_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_1_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_1_router.sv Line: 49
Info (10281): Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object "BYTE_TO_WORD_SHIFT" differs only in case from object "byte_to_word_shift" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 139
Info (10281): Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object "addr_incr" differs only in case from object "ADDR_INCR" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 279
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_008.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_008.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_008.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_008.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_006.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_006.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_006.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_006.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_005.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_005.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_005.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_005.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 49
Warning (10268): Verilog HDL information at pwm.v(27): always construct contains both blocking and non-blocking assignments File: C:/Users/drill/Desktop/HPS_CONTROL_FPGA_LED/pwm.v Line: 27