fpga_only_master.h

#ifndef _ALTERA_FPGA_ONLY_MASTER_H_
#define _ALTERA_FPGA_ONLY_MASTER_H_

/*
 * This file was automatically generated by the swinfo2header utility.
 * 
 * Created from SOPC Builder system 'soc_system' in
 * file './soc_system.sopcinfo'.
 */

/*
 * This file contains macros for module 'fpga_only_master' and devices
 * connected to the following master:
 *   master
 * 
 * Do not include this header file and another header file created for a
 * different module or master group at the same time.
 * Doing so may result in duplicate macro names.
 * Instead, use the system header file which has macros with unique names.
 */

/*
 * Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2'
 * The macros are prefixed with 'ONCHIP_MEMORY2_0_'.
 * The prefix is the slave descriptor.
 */
#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0
#define ONCHIP_MEMORY2_0_BASE 0x0
#define ONCHIP_MEMORY2_0_SPAN 65536
#define ONCHIP_MEMORY2_0_END 0xffff
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE soc_system_onchip_memory2_0
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY2_0_INSTANCE_ID NONE
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE DONT_CARE
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 65536
#define ONCHIP_MEMORY2_0_WRITABLE 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_DAT_SYM 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_HEX 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HAS_BYTE_LANE 0
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 64
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_FILENAME soc_system_onchip_memory2_0

/*
 * Macros for device 'sysid_qsys', class 'altera_avalon_sysid_qsys'
 * The macros are prefixed with 'SYSID_QSYS_'.
 * The prefix is the slave descriptor.
 */
#define SYSID_QSYS_COMPONENT_TYPE altera_avalon_sysid_qsys
#define SYSID_QSYS_COMPONENT_NAME sysid_qsys
#define SYSID_QSYS_BASE 0x10000
#define SYSID_QSYS_SPAN 8
#define SYSID_QSYS_END 0x10007
#define SYSID_QSYS_ID 2899645186
#define SYSID_QSYS_TIMESTAMP 1531462858

/*
 * Macros for device 'led_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'LED_PIO_'.
 * The prefix is the slave descriptor.
 */
#define LED_PIO_COMPONENT_TYPE altera_avalon_pio
#define LED_PIO_COMPONENT_NAME led_pio
#define LED_PIO_BASE 0x10040
#define LED_PIO_SPAN 16
#define LED_PIO_END 0x1004f
#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_DATA_WIDTH 8
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0
#define LED_PIO_EDGE_TYPE NONE
#define LED_PIO_FREQ 50000000
#define LED_PIO_HAS_IN 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_TRI 0
#define LED_PIO_IRQ_TYPE NONE
#define LED_PIO_RESET_VALUE 0

/*
 * Macros for device 'dipsw_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'DIPSW_PIO_'.
 * The prefix is the slave descriptor.
 */
#define DIPSW_PIO_COMPONENT_TYPE altera_avalon_pio
#define DIPSW_PIO_COMPONENT_NAME dipsw_pio
#define DIPSW_PIO_BASE 0x10080
#define DIPSW_PIO_SPAN 16
#define DIPSW_PIO_END 0x1008f
#define DIPSW_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define DIPSW_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define DIPSW_PIO_CAPTURE 1
#define DIPSW_PIO_DATA_WIDTH 4
#define DIPSW_PIO_DO_TEST_BENCH_WIRING 0
#define DIPSW_PIO_DRIVEN_SIM_VALUE 0
#define DIPSW_PIO_EDGE_TYPE ANY
#define DIPSW_PIO_FREQ 50000000
#define DIPSW_PIO_HAS_IN 1
#define DIPSW_PIO_HAS_OUT 0
#define DIPSW_PIO_HAS_TRI 0
#define DIPSW_PIO_IRQ_TYPE EDGE
#define DIPSW_PIO_RESET_VALUE 0

/*
 * Macros for device 'button_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'BUTTON_PIO_'.
 * The prefix is the slave descriptor.
 */
#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio
#define BUTTON_PIO_COMPONENT_NAME button_pio
#define BUTTON_PIO_BASE 0x100c0
#define BUTTON_PIO_SPAN 16
#define BUTTON_PIO_END 0x100cf
#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_DATA_WIDTH 4
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0
#define BUTTON_PIO_EDGE_TYPE FALLING
#define BUTTON_PIO_FREQ 50000000
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_IRQ_TYPE EDGE
#define BUTTON_PIO_RESET_VALUE 0

/*
 * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
 * The macros are prefixed with 'JTAG_UART_'.
 * The prefix is the slave descriptor.
 */
#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
#define JTAG_UART_COMPONENT_NAME jtag_uart
#define JTAG_UART_BASE 0x20000
#define JTAG_UART_SPAN 8
#define JTAG_UART_END 0x20007
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8

/*
 * Macros for device 'gpio_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'GPIO_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define GPIO_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define GPIO_PIO_0_COMPONENT_NAME gpio_pio_0
#define GPIO_PIO_0_BASE 0x20050
#define GPIO_PIO_0_SPAN 16
#define GPIO_PIO_0_END 0x2005f
#define GPIO_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPIO_PIO_0_CAPTURE 0
#define GPIO_PIO_0_DATA_WIDTH 8
#define GPIO_PIO_0_DO_TEST_BENCH_WIRING 0
#define GPIO_PIO_0_DRIVEN_SIM_VALUE 0
#define GPIO_PIO_0_EDGE_TYPE NONE
#define GPIO_PIO_0_FREQ 50000000
#define GPIO_PIO_0_HAS_IN 0
#define GPIO_PIO_0_HAS_OUT 1
#define GPIO_PIO_0_HAS_TRI 0
#define GPIO_PIO_0_IRQ_TYPE NONE
#define GPIO_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'gpio_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'GPIO_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define GPIO_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define GPIO_PIO_1_COMPONENT_NAME gpio_pio_1
#define GPIO_PIO_1_BASE 0x20160
#define GPIO_PIO_1_SPAN 16
#define GPIO_PIO_1_END 0x2016f
#define GPIO_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPIO_PIO_1_CAPTURE 0
#define GPIO_PIO_1_DATA_WIDTH 8
#define GPIO_PIO_1_DO_TEST_BENCH_WIRING 0
#define GPIO_PIO_1_DRIVEN_SIM_VALUE 0
#define GPIO_PIO_1_EDGE_TYPE NONE
#define GPIO_PIO_1_FREQ 50000000
#define GPIO_PIO_1_HAS_IN 0
#define GPIO_PIO_1_HAS_OUT 1
#define GPIO_PIO_1_HAS_TRI 0
#define GPIO_PIO_1_IRQ_TYPE NONE
#define GPIO_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'quad_reset_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_RESET_PIO_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_RESET_PIO_COMPONENT_TYPE altera_avalon_pio
#define QUAD_RESET_PIO_COMPONENT_NAME quad_reset_pio
#define QUAD_RESET_PIO_BASE 0x20270
#define QUAD_RESET_PIO_SPAN 16
#define QUAD_RESET_PIO_END 0x2027f
#define QUAD_RESET_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_RESET_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_RESET_PIO_CAPTURE 0
#define QUAD_RESET_PIO_DATA_WIDTH 32
#define QUAD_RESET_PIO_DO_TEST_BENCH_WIRING 0
#define QUAD_RESET_PIO_DRIVEN_SIM_VALUE 0
#define QUAD_RESET_PIO_EDGE_TYPE NONE
#define QUAD_RESET_PIO_FREQ 50000000
#define QUAD_RESET_PIO_HAS_IN 0
#define QUAD_RESET_PIO_HAS_OUT 1
#define QUAD_RESET_PIO_HAS_TRI 0
#define QUAD_RESET_PIO_IRQ_TYPE NONE
#define QUAD_RESET_PIO_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_0_COMPONENT_NAME quad_pio_0
#define QUAD_PIO_0_BASE 0x20380
#define QUAD_PIO_0_SPAN 16
#define QUAD_PIO_0_END 0x2038f
#define QUAD_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_0_CAPTURE 0
#define QUAD_PIO_0_DATA_WIDTH 32
#define QUAD_PIO_0_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_0_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_0_EDGE_TYPE NONE
#define QUAD_PIO_0_FREQ 50000000
#define QUAD_PIO_0_HAS_IN 1
#define QUAD_PIO_0_HAS_OUT 0
#define QUAD_PIO_0_HAS_TRI 0
#define QUAD_PIO_0_IRQ_TYPE NONE
#define QUAD_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_1_COMPONENT_NAME quad_pio_1
#define QUAD_PIO_1_BASE 0x20490
#define QUAD_PIO_1_SPAN 16
#define QUAD_PIO_1_END 0x2049f
#define QUAD_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_1_CAPTURE 0
#define QUAD_PIO_1_DATA_WIDTH 32
#define QUAD_PIO_1_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_1_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_1_EDGE_TYPE NONE
#define QUAD_PIO_1_FREQ 50000000
#define QUAD_PIO_1_HAS_IN 1
#define QUAD_PIO_1_HAS_OUT 0
#define QUAD_PIO_1_HAS_TRI 0
#define QUAD_PIO_1_IRQ_TYPE NONE
#define QUAD_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_2_COMPONENT_NAME quad_pio_2
#define QUAD_PIO_2_BASE 0x20500
#define QUAD_PIO_2_SPAN 16
#define QUAD_PIO_2_END 0x2050f
#define QUAD_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_2_CAPTURE 0
#define QUAD_PIO_2_DATA_WIDTH 32
#define QUAD_PIO_2_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_2_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_2_EDGE_TYPE NONE
#define QUAD_PIO_2_FREQ 50000000
#define QUAD_PIO_2_HAS_IN 1
#define QUAD_PIO_2_HAS_OUT 0
#define QUAD_PIO_2_HAS_TRI 0
#define QUAD_PIO_2_IRQ_TYPE NONE
#define QUAD_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_3_COMPONENT_NAME quad_pio_3
#define QUAD_PIO_3_BASE 0x20610
#define QUAD_PIO_3_SPAN 16
#define QUAD_PIO_3_END 0x2061f
#define QUAD_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_3_CAPTURE 0
#define QUAD_PIO_3_DATA_WIDTH 32
#define QUAD_PIO_3_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_3_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_3_EDGE_TYPE NONE
#define QUAD_PIO_3_FREQ 50000000
#define QUAD_PIO_3_HAS_IN 1
#define QUAD_PIO_3_HAS_OUT 0
#define QUAD_PIO_3_HAS_TRI 0
#define QUAD_PIO_3_IRQ_TYPE NONE
#define QUAD_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_4_COMPONENT_NAME quad_pio_4
#define QUAD_PIO_4_BASE 0x20720
#define QUAD_PIO_4_SPAN 16
#define QUAD_PIO_4_END 0x2072f
#define QUAD_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_4_CAPTURE 0
#define QUAD_PIO_4_DATA_WIDTH 32
#define QUAD_PIO_4_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_4_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_4_EDGE_TYPE NONE
#define QUAD_PIO_4_FREQ 50000000
#define QUAD_PIO_4_HAS_IN 1
#define QUAD_PIO_4_HAS_OUT 0
#define QUAD_PIO_4_HAS_TRI 0
#define QUAD_PIO_4_IRQ_TYPE NONE
#define QUAD_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_5_COMPONENT_NAME quad_pio_5
#define QUAD_PIO_5_BASE 0x20830
#define QUAD_PIO_5_SPAN 16
#define QUAD_PIO_5_END 0x2083f
#define QUAD_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_5_CAPTURE 0
#define QUAD_PIO_5_DATA_WIDTH 32
#define QUAD_PIO_5_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_5_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_5_EDGE_TYPE NONE
#define QUAD_PIO_5_FREQ 50000000
#define QUAD_PIO_5_HAS_IN 1
#define QUAD_PIO_5_HAS_OUT 0
#define QUAD_PIO_5_HAS_TRI 0
#define QUAD_PIO_5_IRQ_TYPE NONE
#define QUAD_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_6_COMPONENT_NAME quad_pio_6
#define QUAD_PIO_6_BASE 0x20940
#define QUAD_PIO_6_SPAN 16
#define QUAD_PIO_6_END 0x2094f
#define QUAD_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_6_CAPTURE 0
#define QUAD_PIO_6_DATA_WIDTH 32
#define QUAD_PIO_6_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_6_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_6_EDGE_TYPE NONE
#define QUAD_PIO_6_FREQ 50000000
#define QUAD_PIO_6_HAS_IN 1
#define QUAD_PIO_6_HAS_OUT 0
#define QUAD_PIO_6_HAS_TRI 0
#define QUAD_PIO_6_IRQ_TYPE NONE
#define QUAD_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_7_COMPONENT_NAME quad_pio_7
#define QUAD_PIO_7_BASE 0x21050
#define QUAD_PIO_7_SPAN 16
#define QUAD_PIO_7_END 0x2105f
#define QUAD_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_7_CAPTURE 0
#define QUAD_PIO_7_DATA_WIDTH 32
#define QUAD_PIO_7_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_7_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_7_EDGE_TYPE NONE
#define QUAD_PIO_7_FREQ 50000000
#define QUAD_PIO_7_HAS_IN 1
#define QUAD_PIO_7_HAS_OUT 0
#define QUAD_PIO_7_HAS_TRI 0
#define QUAD_PIO_7_IRQ_TYPE NONE
#define QUAD_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_8', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_8_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_8_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_8_COMPONENT_NAME quad_pio_8
#define QUAD_PIO_8_BASE 0x21060
#define QUAD_PIO_8_SPAN 16
#define QUAD_PIO_8_END 0x2106f
#define QUAD_PIO_8_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_8_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_8_CAPTURE 0
#define QUAD_PIO_8_DATA_WIDTH 32
#define QUAD_PIO_8_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_8_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_8_EDGE_TYPE NONE
#define QUAD_PIO_8_FREQ 50000000
#define QUAD_PIO_8_HAS_IN 1
#define QUAD_PIO_8_HAS_OUT 0
#define QUAD_PIO_8_HAS_TRI 0
#define QUAD_PIO_8_IRQ_TYPE NONE
#define QUAD_PIO_8_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_9', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_9_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_9_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_9_COMPONENT_NAME quad_pio_9
#define QUAD_PIO_9_BASE 0x21070
#define QUAD_PIO_9_SPAN 16
#define QUAD_PIO_9_END 0x2107f
#define QUAD_PIO_9_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_9_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_9_CAPTURE 0
#define QUAD_PIO_9_DATA_WIDTH 32
#define QUAD_PIO_9_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_9_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_9_EDGE_TYPE NONE
#define QUAD_PIO_9_FREQ 50000000
#define QUAD_PIO_9_HAS_IN 1
#define QUAD_PIO_9_HAS_OUT 0
#define QUAD_PIO_9_HAS_TRI 0
#define QUAD_PIO_9_IRQ_TYPE NONE
#define QUAD_PIO_9_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_10', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_10_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_10_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_10_COMPONENT_NAME quad_pio_10
#define QUAD_PIO_10_BASE 0x21080
#define QUAD_PIO_10_SPAN 16
#define QUAD_PIO_10_END 0x2108f
#define QUAD_PIO_10_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_10_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_10_CAPTURE 0
#define QUAD_PIO_10_DATA_WIDTH 32
#define QUAD_PIO_10_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_10_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_10_EDGE_TYPE NONE
#define QUAD_PIO_10_FREQ 50000000
#define QUAD_PIO_10_HAS_IN 1
#define QUAD_PIO_10_HAS_OUT 0
#define QUAD_PIO_10_HAS_TRI 0
#define QUAD_PIO_10_IRQ_TYPE NONE
#define QUAD_PIO_10_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_11', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_11_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_11_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_11_COMPONENT_NAME quad_pio_11
#define QUAD_PIO_11_BASE 0x21090
#define QUAD_PIO_11_SPAN 16
#define QUAD_PIO_11_END 0x2109f
#define QUAD_PIO_11_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_11_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_11_CAPTURE 0
#define QUAD_PIO_11_DATA_WIDTH 32
#define QUAD_PIO_11_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_11_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_11_EDGE_TYPE NONE
#define QUAD_PIO_11_FREQ 50000000
#define QUAD_PIO_11_HAS_IN 1
#define QUAD_PIO_11_HAS_OUT 0
#define QUAD_PIO_11_HAS_TRI 0
#define QUAD_PIO_11_IRQ_TYPE NONE
#define QUAD_PIO_11_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_0_COMPONENT_NAME pid_error_pio_0
#define PID_ERROR_PIO_0_BASE 0x21160
#define PID_ERROR_PIO_0_SPAN 16
#define PID_ERROR_PIO_0_END 0x2116f
#define PID_ERROR_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_0_CAPTURE 0
#define PID_ERROR_PIO_0_DATA_WIDTH 32
#define PID_ERROR_PIO_0_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_0_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_0_EDGE_TYPE NONE
#define PID_ERROR_PIO_0_FREQ 50000000
#define PID_ERROR_PIO_0_HAS_IN 0
#define PID_ERROR_PIO_0_HAS_OUT 1
#define PID_ERROR_PIO_0_HAS_TRI 0
#define PID_ERROR_PIO_0_IRQ_TYPE NONE
#define PID_ERROR_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_1_COMPONENT_NAME pid_error_pio_1
#define PID_ERROR_PIO_1_BASE 0x21270
#define PID_ERROR_PIO_1_SPAN 16
#define PID_ERROR_PIO_1_END 0x2127f
#define PID_ERROR_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_1_CAPTURE 0
#define PID_ERROR_PIO_1_DATA_WIDTH 32
#define PID_ERROR_PIO_1_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_1_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_1_EDGE_TYPE NONE
#define PID_ERROR_PIO_1_FREQ 50000000
#define PID_ERROR_PIO_1_HAS_IN 0
#define PID_ERROR_PIO_1_HAS_OUT 1
#define PID_ERROR_PIO_1_HAS_TRI 0
#define PID_ERROR_PIO_1_IRQ_TYPE NONE
#define PID_ERROR_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_2_COMPONENT_NAME pid_error_pio_2
#define PID_ERROR_PIO_2_BASE 0x21380
#define PID_ERROR_PIO_2_SPAN 16
#define PID_ERROR_PIO_2_END 0x2138f
#define PID_ERROR_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_2_CAPTURE 0
#define PID_ERROR_PIO_2_DATA_WIDTH 32
#define PID_ERROR_PIO_2_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_2_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_2_EDGE_TYPE NONE
#define PID_ERROR_PIO_2_FREQ 50000000
#define PID_ERROR_PIO_2_HAS_IN 0
#define PID_ERROR_PIO_2_HAS_OUT 1
#define PID_ERROR_PIO_2_HAS_TRI 0
#define PID_ERROR_PIO_2_IRQ_TYPE NONE
#define PID_ERROR_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_3_COMPONENT_NAME pid_error_pio_3
#define PID_ERROR_PIO_3_BASE 0x21490
#define PID_ERROR_PIO_3_SPAN 16
#define PID_ERROR_PIO_3_END 0x2149f
#define PID_ERROR_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_3_CAPTURE 0
#define PID_ERROR_PIO_3_DATA_WIDTH 32
#define PID_ERROR_PIO_3_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_3_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_3_EDGE_TYPE NONE
#define PID_ERROR_PIO_3_FREQ 50000000
#define PID_ERROR_PIO_3_HAS_IN 0
#define PID_ERROR_PIO_3_HAS_OUT 1
#define PID_ERROR_PIO_3_HAS_TRI 0
#define PID_ERROR_PIO_3_IRQ_TYPE NONE
#define PID_ERROR_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_4_COMPONENT_NAME pid_error_pio_4
#define PID_ERROR_PIO_4_BASE 0x21500
#define PID_ERROR_PIO_4_SPAN 16
#define PID_ERROR_PIO_4_END 0x2150f
#define PID_ERROR_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_4_CAPTURE 0
#define PID_ERROR_PIO_4_DATA_WIDTH 32
#define PID_ERROR_PIO_4_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_4_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_4_EDGE_TYPE NONE
#define PID_ERROR_PIO_4_FREQ 50000000
#define PID_ERROR_PIO_4_HAS_IN 0
#define PID_ERROR_PIO_4_HAS_OUT 1
#define PID_ERROR_PIO_4_HAS_TRI 0
#define PID_ERROR_PIO_4_IRQ_TYPE NONE
#define PID_ERROR_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_5_COMPONENT_NAME pid_error_pio_5
#define PID_ERROR_PIO_5_BASE 0x21620
#define PID_ERROR_PIO_5_SPAN 16
#define PID_ERROR_PIO_5_END 0x2162f
#define PID_ERROR_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_5_CAPTURE 0
#define PID_ERROR_PIO_5_DATA_WIDTH 32
#define PID_ERROR_PIO_5_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_5_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_5_EDGE_TYPE NONE
#define PID_ERROR_PIO_5_FREQ 50000000
#define PID_ERROR_PIO_5_HAS_IN 0
#define PID_ERROR_PIO_5_HAS_OUT 1
#define PID_ERROR_PIO_5_HAS_TRI 0
#define PID_ERROR_PIO_5_IRQ_TYPE NONE
#define PID_ERROR_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_6_COMPONENT_NAME pid_error_pio_6
#define PID_ERROR_PIO_6_BASE 0x21730
#define PID_ERROR_PIO_6_SPAN 16
#define PID_ERROR_PIO_6_END 0x2173f
#define PID_ERROR_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_6_CAPTURE 0
#define PID_ERROR_PIO_6_DATA_WIDTH 32
#define PID_ERROR_PIO_6_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_6_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_6_EDGE_TYPE NONE
#define PID_ERROR_PIO_6_FREQ 50000000
#define PID_ERROR_PIO_6_HAS_IN 0
#define PID_ERROR_PIO_6_HAS_OUT 1
#define PID_ERROR_PIO_6_HAS_TRI 0
#define PID_ERROR_PIO_6_IRQ_TYPE NONE
#define PID_ERROR_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_7_COMPONENT_NAME pid_error_pio_7
#define PID_ERROR_PIO_7_BASE 0x21840
#define PID_ERROR_PIO_7_SPAN 16
#define PID_ERROR_PIO_7_END 0x2184f
#define PID_ERROR_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_7_CAPTURE 0
#define PID_ERROR_PIO_7_DATA_WIDTH 32
#define PID_ERROR_PIO_7_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_7_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_7_EDGE_TYPE NONE
#define PID_ERROR_PIO_7_FREQ 50000000
#define PID_ERROR_PIO_7_HAS_IN 0
#define PID_ERROR_PIO_7_HAS_OUT 1
#define PID_ERROR_PIO_7_HAS_TRI 0
#define PID_ERROR_PIO_7_IRQ_TYPE NONE
#define PID_ERROR_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_0_COMPONENT_NAME pid_correction_pio_0
#define PID_CORRECTION_PIO_0_BASE 0x21950
#define PID_CORRECTION_PIO_0_SPAN 16
#define PID_CORRECTION_PIO_0_END 0x2195f
#define PID_CORRECTION_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_0_CAPTURE 0
#define PID_CORRECTION_PIO_0_DATA_WIDTH 32
#define PID_CORRECTION_PIO_0_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_0_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_0_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_0_FREQ 50000000
#define PID_CORRECTION_PIO_0_HAS_IN 1
#define PID_CORRECTION_PIO_0_HAS_OUT 0
#define PID_CORRECTION_PIO_0_HAS_TRI 0
#define PID_CORRECTION_PIO_0_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_1_COMPONENT_NAME pid_correction_pio_1
#define PID_CORRECTION_PIO_1_BASE 0x22060
#define PID_CORRECTION_PIO_1_SPAN 16
#define PID_CORRECTION_PIO_1_END 0x2206f
#define PID_CORRECTION_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_1_CAPTURE 0
#define PID_CORRECTION_PIO_1_DATA_WIDTH 32
#define PID_CORRECTION_PIO_1_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_1_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_1_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_1_FREQ 50000000
#define PID_CORRECTION_PIO_1_HAS_IN 1
#define PID_CORRECTION_PIO_1_HAS_OUT 0
#define PID_CORRECTION_PIO_1_HAS_TRI 0
#define PID_CORRECTION_PIO_1_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_2_COMPONENT_NAME pid_correction_pio_2
#define PID_CORRECTION_PIO_2_BASE 0x22170
#define PID_CORRECTION_PIO_2_SPAN 16
#define PID_CORRECTION_PIO_2_END 0x2217f
#define PID_CORRECTION_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_2_CAPTURE 0
#define PID_CORRECTION_PIO_2_DATA_WIDTH 32
#define PID_CORRECTION_PIO_2_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_2_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_2_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_2_FREQ 50000000
#define PID_CORRECTION_PIO_2_HAS_IN 1
#define PID_CORRECTION_PIO_2_HAS_OUT 0
#define PID_CORRECTION_PIO_2_HAS_TRI 0
#define PID_CORRECTION_PIO_2_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_3_COMPONENT_NAME pid_correction_pio_3
#define PID_CORRECTION_PIO_3_BASE 0x22280
#define PID_CORRECTION_PIO_3_SPAN 16
#define PID_CORRECTION_PIO_3_END 0x2228f
#define PID_CORRECTION_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_3_CAPTURE 0
#define PID_CORRECTION_PIO_3_DATA_WIDTH 32
#define PID_CORRECTION_PIO_3_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_3_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_3_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_3_FREQ 50000000
#define PID_CORRECTION_PIO_3_HAS_IN 1
#define PID_CORRECTION_PIO_3_HAS_OUT 0
#define PID_CORRECTION_PIO_3_HAS_TRI 0
#define PID_CORRECTION_PIO_3_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_4_COMPONENT_NAME pid_correction_pio_4
#define PID_CORRECTION_PIO_4_BASE 0x22390
#define PID_CORRECTION_PIO_4_SPAN 16
#define PID_CORRECTION_PIO_4_END 0x2239f
#define PID_CORRECTION_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_4_CAPTURE 0
#define PID_CORRECTION_PIO_4_DATA_WIDTH 32
#define PID_CORRECTION_PIO_4_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_4_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_4_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_4_FREQ 50000000
#define PID_CORRECTION_PIO_4_HAS_IN 1
#define PID_CORRECTION_PIO_4_HAS_OUT 0
#define PID_CORRECTION_PIO_4_HAS_TRI 0
#define PID_CORRECTION_PIO_4_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_5_COMPONENT_NAME pid_correction_pio_5
#define PID_CORRECTION_PIO_5_BASE 0x22400
#define PID_CORRECTION_PIO_5_SPAN 16
#define PID_CORRECTION_PIO_5_END 0x2240f
#define PID_CORRECTION_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_5_CAPTURE 0
#define PID_CORRECTION_PIO_5_DATA_WIDTH 32
#define PID_CORRECTION_PIO_5_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_5_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_5_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_5_FREQ 50000000
#define PID_CORRECTION_PIO_5_HAS_IN 1
#define PID_CORRECTION_PIO_5_HAS_OUT 0
#define PID_CORRECTION_PIO_5_HAS_TRI 0
#define PID_CORRECTION_PIO_5_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_6_COMPONENT_NAME pid_correction_pio_6
#define PID_CORRECTION_PIO_6_BASE 0x22510
#define PID_CORRECTION_PIO_6_SPAN 16
#define PID_CORRECTION_PIO_6_END 0x2251f
#define PID_CORRECTION_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_6_CAPTURE 0
#define PID_CORRECTION_PIO_6_DATA_WIDTH 32
#define PID_CORRECTION_PIO_6_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_6_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_6_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_6_FREQ 50000000
#define PID_CORRECTION_PIO_6_HAS_IN 1
#define PID_CORRECTION_PIO_6_HAS_OUT 0
#define PID_CORRECTION_PIO_6_HAS_TRI 0
#define PID_CORRECTION_PIO_6_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_7_COMPONENT_NAME pid_correction_pio_7
#define PID_CORRECTION_PIO_7_BASE 0x22620
#define PID_CORRECTION_PIO_7_SPAN 16
#define PID_CORRECTION_PIO_7_END 0x2262f
#define PID_CORRECTION_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_7_CAPTURE 0
#define PID_CORRECTION_PIO_7_DATA_WIDTH 32
#define PID_CORRECTION_PIO_7_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_7_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_7_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_7_FREQ 50000000
#define PID_CORRECTION_PIO_7_HAS_IN 1
#define PID_CORRECTION_PIO_7_HAS_OUT 0
#define PID_CORRECTION_PIO_7_HAS_TRI 0
#define PID_CORRECTION_PIO_7_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'pid_values_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_VALUES_PIO_'.
 * The prefix is the slave descriptor.
 */
#define PID_VALUES_PIO_COMPONENT_TYPE altera_avalon_pio
#define PID_VALUES_PIO_COMPONENT_NAME pid_values_pio
#define PID_VALUES_PIO_BASE 0x22730
#define PID_VALUES_PIO_SPAN 16
#define PID_VALUES_PIO_END 0x2273f
#define PID_VALUES_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define PID_VALUES_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_VALUES_PIO_CAPTURE 0
#define PID_VALUES_PIO_DATA_WIDTH 32
#define PID_VALUES_PIO_DO_TEST_BENCH_WIRING 0
#define PID_VALUES_PIO_DRIVEN_SIM_VALUE 0
#define PID_VALUES_PIO_EDGE_TYPE NONE
#define PID_VALUES_PIO_FREQ 50000000
#define PID_VALUES_PIO_HAS_IN 0
#define PID_VALUES_PIO_HAS_OUT 1
#define PID_VALUES_PIO_HAS_TRI 0
#define PID_VALUES_PIO_IRQ_TYPE NONE
#define PID_VALUES_PIO_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_0_COMPONENT_NAME pwm_pio_0
#define PWM_PIO_0_BASE 0x22840
#define PWM_PIO_0_SPAN 16
#define PWM_PIO_0_END 0x2284f
#define PWM_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_0_CAPTURE 0
#define PWM_PIO_0_DATA_WIDTH 32
#define PWM_PIO_0_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_0_DRIVEN_SIM_VALUE 0
#define PWM_PIO_0_EDGE_TYPE NONE
#define PWM_PIO_0_FREQ 50000000
#define PWM_PIO_0_HAS_IN 0
#define PWM_PIO_0_HAS_OUT 1
#define PWM_PIO_0_HAS_TRI 0
#define PWM_PIO_0_IRQ_TYPE NONE
#define PWM_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_1_COMPONENT_NAME pwm_pio_1
#define PWM_PIO_1_BASE 0x22950
#define PWM_PIO_1_SPAN 16
#define PWM_PIO_1_END 0x2295f
#define PWM_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_1_CAPTURE 0
#define PWM_PIO_1_DATA_WIDTH 32
#define PWM_PIO_1_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_1_DRIVEN_SIM_VALUE 0
#define PWM_PIO_1_EDGE_TYPE NONE
#define PWM_PIO_1_FREQ 50000000
#define PWM_PIO_1_HAS_IN 0
#define PWM_PIO_1_HAS_OUT 1
#define PWM_PIO_1_HAS_TRI 0
#define PWM_PIO_1_IRQ_TYPE NONE
#define PWM_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_2_COMPONENT_NAME pwm_pio_2
#define PWM_PIO_2_BASE 0x23060
#define PWM_PIO_2_SPAN 16
#define PWM_PIO_2_END 0x2306f
#define PWM_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_2_CAPTURE 0
#define PWM_PIO_2_DATA_WIDTH 32
#define PWM_PIO_2_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_2_DRIVEN_SIM_VALUE 0
#define PWM_PIO_2_EDGE_TYPE NONE
#define PWM_PIO_2_FREQ 50000000
#define PWM_PIO_2_HAS_IN 0
#define PWM_PIO_2_HAS_OUT 1
#define PWM_PIO_2_HAS_TRI 0
#define PWM_PIO_2_IRQ_TYPE NONE
#define PWM_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_3_COMPONENT_NAME pwm_pio_3
#define PWM_PIO_3_BASE 0x23170
#define PWM_PIO_3_SPAN 16
#define PWM_PIO_3_END 0x2317f
#define PWM_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_3_CAPTURE 0
#define PWM_PIO_3_DATA_WIDTH 32
#define PWM_PIO_3_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_3_DRIVEN_SIM_VALUE 0
#define PWM_PIO_3_EDGE_TYPE NONE
#define PWM_PIO_3_FREQ 50000000
#define PWM_PIO_3_HAS_IN 0
#define PWM_PIO_3_HAS_OUT 1
#define PWM_PIO_3_HAS_TRI 0
#define PWM_PIO_3_IRQ_TYPE NONE
#define PWM_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_4_COMPONENT_NAME pwm_pio_4
#define PWM_PIO_4_BASE 0x23280
#define PWM_PIO_4_SPAN 16
#define PWM_PIO_4_END 0x2328f
#define PWM_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_4_CAPTURE 0
#define PWM_PIO_4_DATA_WIDTH 32
#define PWM_PIO_4_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_4_DRIVEN_SIM_VALUE 0
#define PWM_PIO_4_EDGE_TYPE NONE
#define PWM_PIO_4_FREQ 50000000
#define PWM_PIO_4_HAS_IN 0
#define PWM_PIO_4_HAS_OUT 1
#define PWM_PIO_4_HAS_TRI 0
#define PWM_PIO_4_IRQ_TYPE NONE
#define PWM_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_5_COMPONENT_NAME pwm_pio_5
#define PWM_PIO_5_BASE 0x23390
#define PWM_PIO_5_SPAN 16
#define PWM_PIO_5_END 0x2339f
#define PWM_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_5_CAPTURE 0
#define PWM_PIO_5_DATA_WIDTH 32
#define PWM_PIO_5_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_5_DRIVEN_SIM_VALUE 0
#define PWM_PIO_5_EDGE_TYPE NONE
#define PWM_PIO_5_FREQ 50000000
#define PWM_PIO_5_HAS_IN 0
#define PWM_PIO_5_HAS_OUT 1
#define PWM_PIO_5_HAS_TRI 0
#define PWM_PIO_5_IRQ_TYPE NONE
#define PWM_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_6_COMPONENT_NAME pwm_pio_6
#define PWM_PIO_6_BASE 0x23400
#define PWM_PIO_6_SPAN 16
#define PWM_PIO_6_END 0x2340f
#define PWM_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_6_CAPTURE 0
#define PWM_PIO_6_DATA_WIDTH 32
#define PWM_PIO_6_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_6_DRIVEN_SIM_VALUE 0
#define PWM_PIO_6_EDGE_TYPE NONE
#define PWM_PIO_6_FREQ 50000000
#define PWM_PIO_6_HAS_IN 0
#define PWM_PIO_6_HAS_OUT 1
#define PWM_PIO_6_HAS_TRI 0
#define PWM_PIO_6_IRQ_TYPE NONE
#define PWM_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_7_COMPONENT_NAME pwm_pio_7
#define PWM_PIO_7_BASE 0x23510
#define PWM_PIO_7_SPAN 16
#define PWM_PIO_7_END 0x2351f
#define PWM_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_7_CAPTURE 0
#define PWM_PIO_7_DATA_WIDTH 32
#define PWM_PIO_7_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_7_DRIVEN_SIM_VALUE 0
#define PWM_PIO_7_EDGE_TYPE NONE
#define PWM_PIO_7_FREQ 50000000
#define PWM_PIO_7_HAS_IN 0
#define PWM_PIO_7_HAS_OUT 1
#define PWM_PIO_7_HAS_TRI 0
#define PWM_PIO_7_IRQ_TYPE NONE
#define PWM_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'limit_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'LIMIT_PIO_'.
 * The prefix is the slave descriptor.
 */
#define LIMIT_PIO_COMPONENT_TYPE altera_avalon_pio
#define LIMIT_PIO_COMPONENT_NAME limit_pio
#define LIMIT_PIO_BASE 0x23610
#define LIMIT_PIO_SPAN 16
#define LIMIT_PIO_END 0x2361f
#define LIMIT_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LIMIT_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LIMIT_PIO_CAPTURE 0
#define LIMIT_PIO_DATA_WIDTH 8
#define LIMIT_PIO_DO_TEST_BENCH_WIRING 0
#define LIMIT_PIO_DRIVEN_SIM_VALUE 0
#define LIMIT_PIO_EDGE_TYPE NONE
#define LIMIT_PIO_FREQ 50000000
#define LIMIT_PIO_HAS_IN 1
#define LIMIT_PIO_HAS_OUT 0
#define LIMIT_PIO_HAS_TRI 0
#define LIMIT_PIO_IRQ_TYPE NONE
#define LIMIT_PIO_RESET_VALUE 0

/*
 * Macros for device 'heartbeat', class 'altera_avalon_pio'
 * The macros are prefixed with 'HEARTBEAT_'.
 * The prefix is the slave descriptor.
 */
#define HEARTBEAT_COMPONENT_TYPE altera_avalon_pio
#define HEARTBEAT_COMPONENT_NAME heartbeat
#define HEARTBEAT_BASE 0x23710
#define HEARTBEAT_SPAN 16
#define HEARTBEAT_END 0x2371f
#define HEARTBEAT_BIT_CLEARING_EDGE_REGISTER 0
#define HEARTBEAT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HEARTBEAT_CAPTURE 0
#define HEARTBEAT_DATA_WIDTH 32
#define HEARTBEAT_DO_TEST_BENCH_WIRING 0
#define HEARTBEAT_DRIVEN_SIM_VALUE 0
#define HEARTBEAT_EDGE_TYPE NONE
#define HEARTBEAT_FREQ 50000000
#define HEARTBEAT_HAS_IN 0
#define HEARTBEAT_HAS_OUT 1
#define HEARTBEAT_HAS_TRI 0
#define HEARTBEAT_IRQ_TYPE NONE
#define HEARTBEAT_RESET_VALUE 0

/*
 * Macros for device 'e_stop', class 'altera_avalon_pio'
 * The macros are prefixed with 'E_STOP_'.
 * The prefix is the slave descriptor.
 */
#define E_STOP_COMPONENT_TYPE altera_avalon_pio
#define E_STOP_COMPONENT_NAME e_stop
#define E_STOP_BASE 0x23810
#define E_STOP_SPAN 16
#define E_STOP_END 0x2381f
#define E_STOP_BIT_CLEARING_EDGE_REGISTER 0
#define E_STOP_BIT_MODIFYING_OUTPUT_REGISTER 0
#define E_STOP_CAPTURE 0
#define E_STOP_DATA_WIDTH 1
#define E_STOP_DO_TEST_BENCH_WIRING 0
#define E_STOP_DRIVEN_SIM_VALUE 0
#define E_STOP_EDGE_TYPE NONE
#define E_STOP_FREQ 50000000
#define E_STOP_HAS_IN 1
#define E_STOP_HAS_OUT 0
#define E_STOP_HAS_TRI 0
#define E_STOP_IRQ_TYPE NONE
#define E_STOP_RESET_VALUE 0

/*
 * Macros for device 'adc_0', class 'altera_up_avalon_adc'
 * The macros are prefixed with 'ADC_0_'.
 * The prefix is the slave descriptor.
 */
#define ADC_0_COMPONENT_TYPE altera_up_avalon_adc
#define ADC_0_COMPONENT_NAME adc_0
#define ADC_0_BASE 0x23900
#define ADC_0_SPAN 32
#define ADC_0_END 0x2391f

/*
 * Macros for device 'intr_capturer_0', class 'intr_capturer'
 * The macros are prefixed with 'INTR_CAPTURER_0_'.
 * The prefix is the slave descriptor.
 */
#define INTR_CAPTURER_0_COMPONENT_TYPE intr_capturer
#define INTR_CAPTURER_0_COMPONENT_NAME intr_capturer_0
#define INTR_CAPTURER_0_BASE 0x30000
#define INTR_CAPTURER_0_SPAN 8
#define INTR_CAPTURER_0_END 0x30007


#endif /* _ALTERA_FPGA_ONLY_MASTER_H_ */