hps_0_arm_a9_1.h

#ifndef _ALTERA_HPS_0_ARM_A9_1_H_
#define _ALTERA_HPS_0_ARM_A9_1_H_

/*
 * This file was automatically generated by the swinfo2header utility.
 * 
 * Created from SOPC Builder system 'soc_system' in
 * file './soc_system.sopcinfo'.
 */

/*
 * This file contains macros for module 'hps_0_arm_a9_1' and devices
 * connected to the following master:
 *   altera_axi_master
 * 
 * Do not include this header file and another header file created for a
 * different module or master group at the same time.
 * Doing so may result in duplicate macro names.
 * Instead, use the system header file which has macros with unique names.
 */

/*
 * Macros for device 'hps_0_axi_sdram', class 'axi_sdram'
 * The macros are prefixed with 'HPS_0_AXI_SDRAM_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_AXI_SDRAM_COMPONENT_TYPE axi_sdram
#define HPS_0_AXI_SDRAM_COMPONENT_NAME hps_0_axi_sdram
#define HPS_0_AXI_SDRAM_BASE 0x0
#define HPS_0_AXI_SDRAM_SPAN 0x80000000
#define HPS_0_AXI_SDRAM_END 0x7fffffff
#define HPS_0_AXI_SDRAM_SIZE_MULTIPLE 1
#define HPS_0_AXI_SDRAM_SIZE_VALUE 1<<31
#define HPS_0_AXI_SDRAM_WRITABLE 1
#define HPS_0_AXI_SDRAM_MEMORY_INFO_GENERATE_DAT_SYM 0
#define HPS_0_AXI_SDRAM_MEMORY_INFO_GENERATE_HEX 0
#define HPS_0_AXI_SDRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 31

/*
 * Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2'
 * The macros are prefixed with 'ONCHIP_MEMORY2_0_'.
 * The prefix is the slave descriptor.
 */
#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0
#define ONCHIP_MEMORY2_0_BASE 0xc0000000
#define ONCHIP_MEMORY2_0_SPAN 65536
#define ONCHIP_MEMORY2_0_END 0xc000ffff
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE soc_system_onchip_memory2_0
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY2_0_INSTANCE_ID NONE
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE DONT_CARE
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 65536
#define ONCHIP_MEMORY2_0_WRITABLE 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_DAT_SYM 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_HEX 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HAS_BYTE_LANE 0
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 64
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_FILENAME soc_system_onchip_memory2_0

/*
 * Macros for device 'sysid_qsys', class 'altera_avalon_sysid_qsys'
 * The macros are prefixed with 'SYSID_QSYS_'.
 * The prefix is the slave descriptor.
 */
#define SYSID_QSYS_COMPONENT_TYPE altera_avalon_sysid_qsys
#define SYSID_QSYS_COMPONENT_NAME sysid_qsys
#define SYSID_QSYS_BASE 0xff210000
#define SYSID_QSYS_SPAN 8
#define SYSID_QSYS_END 0xff210007
#define SYSID_QSYS_ID 2899645186
#define SYSID_QSYS_TIMESTAMP 1531462858

/*
 * Macros for device 'led_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'LED_PIO_'.
 * The prefix is the slave descriptor.
 */
#define LED_PIO_COMPONENT_TYPE altera_avalon_pio
#define LED_PIO_COMPONENT_NAME led_pio
#define LED_PIO_BASE 0xff210040
#define LED_PIO_SPAN 16
#define LED_PIO_END 0xff21004f
#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_DATA_WIDTH 8
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0
#define LED_PIO_EDGE_TYPE NONE
#define LED_PIO_FREQ 50000000
#define LED_PIO_HAS_IN 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_TRI 0
#define LED_PIO_IRQ_TYPE NONE
#define LED_PIO_RESET_VALUE 0

/*
 * Macros for device 'dipsw_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'DIPSW_PIO_'.
 * The prefix is the slave descriptor.
 */
#define DIPSW_PIO_COMPONENT_TYPE altera_avalon_pio
#define DIPSW_PIO_COMPONENT_NAME dipsw_pio
#define DIPSW_PIO_BASE 0xff210080
#define DIPSW_PIO_SPAN 16
#define DIPSW_PIO_END 0xff21008f
#define DIPSW_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define DIPSW_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define DIPSW_PIO_CAPTURE 1
#define DIPSW_PIO_DATA_WIDTH 4
#define DIPSW_PIO_DO_TEST_BENCH_WIRING 0
#define DIPSW_PIO_DRIVEN_SIM_VALUE 0
#define DIPSW_PIO_EDGE_TYPE ANY
#define DIPSW_PIO_FREQ 50000000
#define DIPSW_PIO_HAS_IN 1
#define DIPSW_PIO_HAS_OUT 0
#define DIPSW_PIO_HAS_TRI 0
#define DIPSW_PIO_IRQ_TYPE EDGE
#define DIPSW_PIO_RESET_VALUE 0

/*
 * Macros for device 'button_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'BUTTON_PIO_'.
 * The prefix is the slave descriptor.
 */
#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio
#define BUTTON_PIO_COMPONENT_NAME button_pio
#define BUTTON_PIO_BASE 0xff2100c0
#define BUTTON_PIO_SPAN 16
#define BUTTON_PIO_END 0xff2100cf
#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_DATA_WIDTH 4
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0
#define BUTTON_PIO_EDGE_TYPE FALLING
#define BUTTON_PIO_FREQ 50000000
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_IRQ_TYPE EDGE
#define BUTTON_PIO_RESET_VALUE 0

/*
 * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
 * The macros are prefixed with 'JTAG_UART_'.
 * The prefix is the slave descriptor.
 */
#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
#define JTAG_UART_COMPONENT_NAME jtag_uart
#define JTAG_UART_BASE 0xff220000
#define JTAG_UART_SPAN 8
#define JTAG_UART_END 0xff220007
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8

/*
 * Macros for device 'gpio_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'GPIO_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define GPIO_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define GPIO_PIO_0_COMPONENT_NAME gpio_pio_0
#define GPIO_PIO_0_BASE 0xff220050
#define GPIO_PIO_0_SPAN 16
#define GPIO_PIO_0_END 0xff22005f
#define GPIO_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPIO_PIO_0_CAPTURE 0
#define GPIO_PIO_0_DATA_WIDTH 8
#define GPIO_PIO_0_DO_TEST_BENCH_WIRING 0
#define GPIO_PIO_0_DRIVEN_SIM_VALUE 0
#define GPIO_PIO_0_EDGE_TYPE NONE
#define GPIO_PIO_0_FREQ 50000000
#define GPIO_PIO_0_HAS_IN 0
#define GPIO_PIO_0_HAS_OUT 1
#define GPIO_PIO_0_HAS_TRI 0
#define GPIO_PIO_0_IRQ_TYPE NONE
#define GPIO_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'gpio_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'GPIO_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define GPIO_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define GPIO_PIO_1_COMPONENT_NAME gpio_pio_1
#define GPIO_PIO_1_BASE 0xff220160
#define GPIO_PIO_1_SPAN 16
#define GPIO_PIO_1_END 0xff22016f
#define GPIO_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPIO_PIO_1_CAPTURE 0
#define GPIO_PIO_1_DATA_WIDTH 8
#define GPIO_PIO_1_DO_TEST_BENCH_WIRING 0
#define GPIO_PIO_1_DRIVEN_SIM_VALUE 0
#define GPIO_PIO_1_EDGE_TYPE NONE
#define GPIO_PIO_1_FREQ 50000000
#define GPIO_PIO_1_HAS_IN 0
#define GPIO_PIO_1_HAS_OUT 1
#define GPIO_PIO_1_HAS_TRI 0
#define GPIO_PIO_1_IRQ_TYPE NONE
#define GPIO_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'quad_reset_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_RESET_PIO_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_RESET_PIO_COMPONENT_TYPE altera_avalon_pio
#define QUAD_RESET_PIO_COMPONENT_NAME quad_reset_pio
#define QUAD_RESET_PIO_BASE 0xff220270
#define QUAD_RESET_PIO_SPAN 16
#define QUAD_RESET_PIO_END 0xff22027f
#define QUAD_RESET_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_RESET_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_RESET_PIO_CAPTURE 0
#define QUAD_RESET_PIO_DATA_WIDTH 32
#define QUAD_RESET_PIO_DO_TEST_BENCH_WIRING 0
#define QUAD_RESET_PIO_DRIVEN_SIM_VALUE 0
#define QUAD_RESET_PIO_EDGE_TYPE NONE
#define QUAD_RESET_PIO_FREQ 50000000
#define QUAD_RESET_PIO_HAS_IN 0
#define QUAD_RESET_PIO_HAS_OUT 1
#define QUAD_RESET_PIO_HAS_TRI 0
#define QUAD_RESET_PIO_IRQ_TYPE NONE
#define QUAD_RESET_PIO_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_0_COMPONENT_NAME quad_pio_0
#define QUAD_PIO_0_BASE 0xff220380
#define QUAD_PIO_0_SPAN 16
#define QUAD_PIO_0_END 0xff22038f
#define QUAD_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_0_CAPTURE 0
#define QUAD_PIO_0_DATA_WIDTH 32
#define QUAD_PIO_0_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_0_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_0_EDGE_TYPE NONE
#define QUAD_PIO_0_FREQ 50000000
#define QUAD_PIO_0_HAS_IN 1
#define QUAD_PIO_0_HAS_OUT 0
#define QUAD_PIO_0_HAS_TRI 0
#define QUAD_PIO_0_IRQ_TYPE NONE
#define QUAD_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_1_COMPONENT_NAME quad_pio_1
#define QUAD_PIO_1_BASE 0xff220490
#define QUAD_PIO_1_SPAN 16
#define QUAD_PIO_1_END 0xff22049f
#define QUAD_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_1_CAPTURE 0
#define QUAD_PIO_1_DATA_WIDTH 32
#define QUAD_PIO_1_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_1_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_1_EDGE_TYPE NONE
#define QUAD_PIO_1_FREQ 50000000
#define QUAD_PIO_1_HAS_IN 1
#define QUAD_PIO_1_HAS_OUT 0
#define QUAD_PIO_1_HAS_TRI 0
#define QUAD_PIO_1_IRQ_TYPE NONE
#define QUAD_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_2_COMPONENT_NAME quad_pio_2
#define QUAD_PIO_2_BASE 0xff220500
#define QUAD_PIO_2_SPAN 16
#define QUAD_PIO_2_END 0xff22050f
#define QUAD_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_2_CAPTURE 0
#define QUAD_PIO_2_DATA_WIDTH 32
#define QUAD_PIO_2_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_2_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_2_EDGE_TYPE NONE
#define QUAD_PIO_2_FREQ 50000000
#define QUAD_PIO_2_HAS_IN 1
#define QUAD_PIO_2_HAS_OUT 0
#define QUAD_PIO_2_HAS_TRI 0
#define QUAD_PIO_2_IRQ_TYPE NONE
#define QUAD_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_3_COMPONENT_NAME quad_pio_3
#define QUAD_PIO_3_BASE 0xff220610
#define QUAD_PIO_3_SPAN 16
#define QUAD_PIO_3_END 0xff22061f
#define QUAD_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_3_CAPTURE 0
#define QUAD_PIO_3_DATA_WIDTH 32
#define QUAD_PIO_3_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_3_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_3_EDGE_TYPE NONE
#define QUAD_PIO_3_FREQ 50000000
#define QUAD_PIO_3_HAS_IN 1
#define QUAD_PIO_3_HAS_OUT 0
#define QUAD_PIO_3_HAS_TRI 0
#define QUAD_PIO_3_IRQ_TYPE NONE
#define QUAD_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_4_COMPONENT_NAME quad_pio_4
#define QUAD_PIO_4_BASE 0xff220720
#define QUAD_PIO_4_SPAN 16
#define QUAD_PIO_4_END 0xff22072f
#define QUAD_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_4_CAPTURE 0
#define QUAD_PIO_4_DATA_WIDTH 32
#define QUAD_PIO_4_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_4_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_4_EDGE_TYPE NONE
#define QUAD_PIO_4_FREQ 50000000
#define QUAD_PIO_4_HAS_IN 1
#define QUAD_PIO_4_HAS_OUT 0
#define QUAD_PIO_4_HAS_TRI 0
#define QUAD_PIO_4_IRQ_TYPE NONE
#define QUAD_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_5_COMPONENT_NAME quad_pio_5
#define QUAD_PIO_5_BASE 0xff220830
#define QUAD_PIO_5_SPAN 16
#define QUAD_PIO_5_END 0xff22083f
#define QUAD_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_5_CAPTURE 0
#define QUAD_PIO_5_DATA_WIDTH 32
#define QUAD_PIO_5_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_5_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_5_EDGE_TYPE NONE
#define QUAD_PIO_5_FREQ 50000000
#define QUAD_PIO_5_HAS_IN 1
#define QUAD_PIO_5_HAS_OUT 0
#define QUAD_PIO_5_HAS_TRI 0
#define QUAD_PIO_5_IRQ_TYPE NONE
#define QUAD_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_6_COMPONENT_NAME quad_pio_6
#define QUAD_PIO_6_BASE 0xff220940
#define QUAD_PIO_6_SPAN 16
#define QUAD_PIO_6_END 0xff22094f
#define QUAD_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_6_CAPTURE 0
#define QUAD_PIO_6_DATA_WIDTH 32
#define QUAD_PIO_6_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_6_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_6_EDGE_TYPE NONE
#define QUAD_PIO_6_FREQ 50000000
#define QUAD_PIO_6_HAS_IN 1
#define QUAD_PIO_6_HAS_OUT 0
#define QUAD_PIO_6_HAS_TRI 0
#define QUAD_PIO_6_IRQ_TYPE NONE
#define QUAD_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_7_COMPONENT_NAME quad_pio_7
#define QUAD_PIO_7_BASE 0xff221050
#define QUAD_PIO_7_SPAN 16
#define QUAD_PIO_7_END 0xff22105f
#define QUAD_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_7_CAPTURE 0
#define QUAD_PIO_7_DATA_WIDTH 32
#define QUAD_PIO_7_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_7_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_7_EDGE_TYPE NONE
#define QUAD_PIO_7_FREQ 50000000
#define QUAD_PIO_7_HAS_IN 1
#define QUAD_PIO_7_HAS_OUT 0
#define QUAD_PIO_7_HAS_TRI 0
#define QUAD_PIO_7_IRQ_TYPE NONE
#define QUAD_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_8', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_8_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_8_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_8_COMPONENT_NAME quad_pio_8
#define QUAD_PIO_8_BASE 0xff221060
#define QUAD_PIO_8_SPAN 16
#define QUAD_PIO_8_END 0xff22106f
#define QUAD_PIO_8_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_8_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_8_CAPTURE 0
#define QUAD_PIO_8_DATA_WIDTH 32
#define QUAD_PIO_8_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_8_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_8_EDGE_TYPE NONE
#define QUAD_PIO_8_FREQ 50000000
#define QUAD_PIO_8_HAS_IN 1
#define QUAD_PIO_8_HAS_OUT 0
#define QUAD_PIO_8_HAS_TRI 0
#define QUAD_PIO_8_IRQ_TYPE NONE
#define QUAD_PIO_8_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_9', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_9_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_9_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_9_COMPONENT_NAME quad_pio_9
#define QUAD_PIO_9_BASE 0xff221070
#define QUAD_PIO_9_SPAN 16
#define QUAD_PIO_9_END 0xff22107f
#define QUAD_PIO_9_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_9_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_9_CAPTURE 0
#define QUAD_PIO_9_DATA_WIDTH 32
#define QUAD_PIO_9_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_9_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_9_EDGE_TYPE NONE
#define QUAD_PIO_9_FREQ 50000000
#define QUAD_PIO_9_HAS_IN 1
#define QUAD_PIO_9_HAS_OUT 0
#define QUAD_PIO_9_HAS_TRI 0
#define QUAD_PIO_9_IRQ_TYPE NONE
#define QUAD_PIO_9_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_10', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_10_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_10_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_10_COMPONENT_NAME quad_pio_10
#define QUAD_PIO_10_BASE 0xff221080
#define QUAD_PIO_10_SPAN 16
#define QUAD_PIO_10_END 0xff22108f
#define QUAD_PIO_10_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_10_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_10_CAPTURE 0
#define QUAD_PIO_10_DATA_WIDTH 32
#define QUAD_PIO_10_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_10_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_10_EDGE_TYPE NONE
#define QUAD_PIO_10_FREQ 50000000
#define QUAD_PIO_10_HAS_IN 1
#define QUAD_PIO_10_HAS_OUT 0
#define QUAD_PIO_10_HAS_TRI 0
#define QUAD_PIO_10_IRQ_TYPE NONE
#define QUAD_PIO_10_RESET_VALUE 0

/*
 * Macros for device 'quad_pio_11', class 'altera_avalon_pio'
 * The macros are prefixed with 'QUAD_PIO_11_'.
 * The prefix is the slave descriptor.
 */
#define QUAD_PIO_11_COMPONENT_TYPE altera_avalon_pio
#define QUAD_PIO_11_COMPONENT_NAME quad_pio_11
#define QUAD_PIO_11_BASE 0xff221090
#define QUAD_PIO_11_SPAN 16
#define QUAD_PIO_11_END 0xff22109f
#define QUAD_PIO_11_BIT_CLEARING_EDGE_REGISTER 0
#define QUAD_PIO_11_BIT_MODIFYING_OUTPUT_REGISTER 0
#define QUAD_PIO_11_CAPTURE 0
#define QUAD_PIO_11_DATA_WIDTH 32
#define QUAD_PIO_11_DO_TEST_BENCH_WIRING 0
#define QUAD_PIO_11_DRIVEN_SIM_VALUE 0
#define QUAD_PIO_11_EDGE_TYPE NONE
#define QUAD_PIO_11_FREQ 50000000
#define QUAD_PIO_11_HAS_IN 1
#define QUAD_PIO_11_HAS_OUT 0
#define QUAD_PIO_11_HAS_TRI 0
#define QUAD_PIO_11_IRQ_TYPE NONE
#define QUAD_PIO_11_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_0_COMPONENT_NAME pid_error_pio_0
#define PID_ERROR_PIO_0_BASE 0xff221160
#define PID_ERROR_PIO_0_SPAN 16
#define PID_ERROR_PIO_0_END 0xff22116f
#define PID_ERROR_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_0_CAPTURE 0
#define PID_ERROR_PIO_0_DATA_WIDTH 32
#define PID_ERROR_PIO_0_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_0_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_0_EDGE_TYPE NONE
#define PID_ERROR_PIO_0_FREQ 50000000
#define PID_ERROR_PIO_0_HAS_IN 0
#define PID_ERROR_PIO_0_HAS_OUT 1
#define PID_ERROR_PIO_0_HAS_TRI 0
#define PID_ERROR_PIO_0_IRQ_TYPE NONE
#define PID_ERROR_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_1_COMPONENT_NAME pid_error_pio_1
#define PID_ERROR_PIO_1_BASE 0xff221270
#define PID_ERROR_PIO_1_SPAN 16
#define PID_ERROR_PIO_1_END 0xff22127f
#define PID_ERROR_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_1_CAPTURE 0
#define PID_ERROR_PIO_1_DATA_WIDTH 32
#define PID_ERROR_PIO_1_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_1_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_1_EDGE_TYPE NONE
#define PID_ERROR_PIO_1_FREQ 50000000
#define PID_ERROR_PIO_1_HAS_IN 0
#define PID_ERROR_PIO_1_HAS_OUT 1
#define PID_ERROR_PIO_1_HAS_TRI 0
#define PID_ERROR_PIO_1_IRQ_TYPE NONE
#define PID_ERROR_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_2_COMPONENT_NAME pid_error_pio_2
#define PID_ERROR_PIO_2_BASE 0xff221380
#define PID_ERROR_PIO_2_SPAN 16
#define PID_ERROR_PIO_2_END 0xff22138f
#define PID_ERROR_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_2_CAPTURE 0
#define PID_ERROR_PIO_2_DATA_WIDTH 32
#define PID_ERROR_PIO_2_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_2_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_2_EDGE_TYPE NONE
#define PID_ERROR_PIO_2_FREQ 50000000
#define PID_ERROR_PIO_2_HAS_IN 0
#define PID_ERROR_PIO_2_HAS_OUT 1
#define PID_ERROR_PIO_2_HAS_TRI 0
#define PID_ERROR_PIO_2_IRQ_TYPE NONE
#define PID_ERROR_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_3_COMPONENT_NAME pid_error_pio_3
#define PID_ERROR_PIO_3_BASE 0xff221490
#define PID_ERROR_PIO_3_SPAN 16
#define PID_ERROR_PIO_3_END 0xff22149f
#define PID_ERROR_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_3_CAPTURE 0
#define PID_ERROR_PIO_3_DATA_WIDTH 32
#define PID_ERROR_PIO_3_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_3_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_3_EDGE_TYPE NONE
#define PID_ERROR_PIO_3_FREQ 50000000
#define PID_ERROR_PIO_3_HAS_IN 0
#define PID_ERROR_PIO_3_HAS_OUT 1
#define PID_ERROR_PIO_3_HAS_TRI 0
#define PID_ERROR_PIO_3_IRQ_TYPE NONE
#define PID_ERROR_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_4_COMPONENT_NAME pid_error_pio_4
#define PID_ERROR_PIO_4_BASE 0xff221500
#define PID_ERROR_PIO_4_SPAN 16
#define PID_ERROR_PIO_4_END 0xff22150f
#define PID_ERROR_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_4_CAPTURE 0
#define PID_ERROR_PIO_4_DATA_WIDTH 32
#define PID_ERROR_PIO_4_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_4_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_4_EDGE_TYPE NONE
#define PID_ERROR_PIO_4_FREQ 50000000
#define PID_ERROR_PIO_4_HAS_IN 0
#define PID_ERROR_PIO_4_HAS_OUT 1
#define PID_ERROR_PIO_4_HAS_TRI 0
#define PID_ERROR_PIO_4_IRQ_TYPE NONE
#define PID_ERROR_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_5_COMPONENT_NAME pid_error_pio_5
#define PID_ERROR_PIO_5_BASE 0xff221620
#define PID_ERROR_PIO_5_SPAN 16
#define PID_ERROR_PIO_5_END 0xff22162f
#define PID_ERROR_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_5_CAPTURE 0
#define PID_ERROR_PIO_5_DATA_WIDTH 32
#define PID_ERROR_PIO_5_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_5_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_5_EDGE_TYPE NONE
#define PID_ERROR_PIO_5_FREQ 50000000
#define PID_ERROR_PIO_5_HAS_IN 0
#define PID_ERROR_PIO_5_HAS_OUT 1
#define PID_ERROR_PIO_5_HAS_TRI 0
#define PID_ERROR_PIO_5_IRQ_TYPE NONE
#define PID_ERROR_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_6_COMPONENT_NAME pid_error_pio_6
#define PID_ERROR_PIO_6_BASE 0xff221730
#define PID_ERROR_PIO_6_SPAN 16
#define PID_ERROR_PIO_6_END 0xff22173f
#define PID_ERROR_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_6_CAPTURE 0
#define PID_ERROR_PIO_6_DATA_WIDTH 32
#define PID_ERROR_PIO_6_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_6_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_6_EDGE_TYPE NONE
#define PID_ERROR_PIO_6_FREQ 50000000
#define PID_ERROR_PIO_6_HAS_IN 0
#define PID_ERROR_PIO_6_HAS_OUT 1
#define PID_ERROR_PIO_6_HAS_TRI 0
#define PID_ERROR_PIO_6_IRQ_TYPE NONE
#define PID_ERROR_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'pid_error_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_ERROR_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define PID_ERROR_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define PID_ERROR_PIO_7_COMPONENT_NAME pid_error_pio_7
#define PID_ERROR_PIO_7_BASE 0xff221840
#define PID_ERROR_PIO_7_SPAN 16
#define PID_ERROR_PIO_7_END 0xff22184f
#define PID_ERROR_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PID_ERROR_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_ERROR_PIO_7_CAPTURE 0
#define PID_ERROR_PIO_7_DATA_WIDTH 32
#define PID_ERROR_PIO_7_DO_TEST_BENCH_WIRING 0
#define PID_ERROR_PIO_7_DRIVEN_SIM_VALUE 0
#define PID_ERROR_PIO_7_EDGE_TYPE NONE
#define PID_ERROR_PIO_7_FREQ 50000000
#define PID_ERROR_PIO_7_HAS_IN 0
#define PID_ERROR_PIO_7_HAS_OUT 1
#define PID_ERROR_PIO_7_HAS_TRI 0
#define PID_ERROR_PIO_7_IRQ_TYPE NONE
#define PID_ERROR_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_0_COMPONENT_NAME pid_correction_pio_0
#define PID_CORRECTION_PIO_0_BASE 0xff221950
#define PID_CORRECTION_PIO_0_SPAN 16
#define PID_CORRECTION_PIO_0_END 0xff22195f
#define PID_CORRECTION_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_0_CAPTURE 0
#define PID_CORRECTION_PIO_0_DATA_WIDTH 32
#define PID_CORRECTION_PIO_0_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_0_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_0_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_0_FREQ 50000000
#define PID_CORRECTION_PIO_0_HAS_IN 1
#define PID_CORRECTION_PIO_0_HAS_OUT 0
#define PID_CORRECTION_PIO_0_HAS_TRI 0
#define PID_CORRECTION_PIO_0_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_1_COMPONENT_NAME pid_correction_pio_1
#define PID_CORRECTION_PIO_1_BASE 0xff222060
#define PID_CORRECTION_PIO_1_SPAN 16
#define PID_CORRECTION_PIO_1_END 0xff22206f
#define PID_CORRECTION_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_1_CAPTURE 0
#define PID_CORRECTION_PIO_1_DATA_WIDTH 32
#define PID_CORRECTION_PIO_1_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_1_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_1_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_1_FREQ 50000000
#define PID_CORRECTION_PIO_1_HAS_IN 1
#define PID_CORRECTION_PIO_1_HAS_OUT 0
#define PID_CORRECTION_PIO_1_HAS_TRI 0
#define PID_CORRECTION_PIO_1_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_2_COMPONENT_NAME pid_correction_pio_2
#define PID_CORRECTION_PIO_2_BASE 0xff222170
#define PID_CORRECTION_PIO_2_SPAN 16
#define PID_CORRECTION_PIO_2_END 0xff22217f
#define PID_CORRECTION_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_2_CAPTURE 0
#define PID_CORRECTION_PIO_2_DATA_WIDTH 32
#define PID_CORRECTION_PIO_2_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_2_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_2_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_2_FREQ 50000000
#define PID_CORRECTION_PIO_2_HAS_IN 1
#define PID_CORRECTION_PIO_2_HAS_OUT 0
#define PID_CORRECTION_PIO_2_HAS_TRI 0
#define PID_CORRECTION_PIO_2_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_3_COMPONENT_NAME pid_correction_pio_3
#define PID_CORRECTION_PIO_3_BASE 0xff222280
#define PID_CORRECTION_PIO_3_SPAN 16
#define PID_CORRECTION_PIO_3_END 0xff22228f
#define PID_CORRECTION_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_3_CAPTURE 0
#define PID_CORRECTION_PIO_3_DATA_WIDTH 32
#define PID_CORRECTION_PIO_3_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_3_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_3_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_3_FREQ 50000000
#define PID_CORRECTION_PIO_3_HAS_IN 1
#define PID_CORRECTION_PIO_3_HAS_OUT 0
#define PID_CORRECTION_PIO_3_HAS_TRI 0
#define PID_CORRECTION_PIO_3_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_4_COMPONENT_NAME pid_correction_pio_4
#define PID_CORRECTION_PIO_4_BASE 0xff222390
#define PID_CORRECTION_PIO_4_SPAN 16
#define PID_CORRECTION_PIO_4_END 0xff22239f
#define PID_CORRECTION_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_4_CAPTURE 0
#define PID_CORRECTION_PIO_4_DATA_WIDTH 32
#define PID_CORRECTION_PIO_4_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_4_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_4_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_4_FREQ 50000000
#define PID_CORRECTION_PIO_4_HAS_IN 1
#define PID_CORRECTION_PIO_4_HAS_OUT 0
#define PID_CORRECTION_PIO_4_HAS_TRI 0
#define PID_CORRECTION_PIO_4_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_5_COMPONENT_NAME pid_correction_pio_5
#define PID_CORRECTION_PIO_5_BASE 0xff222400
#define PID_CORRECTION_PIO_5_SPAN 16
#define PID_CORRECTION_PIO_5_END 0xff22240f
#define PID_CORRECTION_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_5_CAPTURE 0
#define PID_CORRECTION_PIO_5_DATA_WIDTH 32
#define PID_CORRECTION_PIO_5_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_5_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_5_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_5_FREQ 50000000
#define PID_CORRECTION_PIO_5_HAS_IN 1
#define PID_CORRECTION_PIO_5_HAS_OUT 0
#define PID_CORRECTION_PIO_5_HAS_TRI 0
#define PID_CORRECTION_PIO_5_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_6_COMPONENT_NAME pid_correction_pio_6
#define PID_CORRECTION_PIO_6_BASE 0xff222510
#define PID_CORRECTION_PIO_6_SPAN 16
#define PID_CORRECTION_PIO_6_END 0xff22251f
#define PID_CORRECTION_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_6_CAPTURE 0
#define PID_CORRECTION_PIO_6_DATA_WIDTH 32
#define PID_CORRECTION_PIO_6_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_6_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_6_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_6_FREQ 50000000
#define PID_CORRECTION_PIO_6_HAS_IN 1
#define PID_CORRECTION_PIO_6_HAS_OUT 0
#define PID_CORRECTION_PIO_6_HAS_TRI 0
#define PID_CORRECTION_PIO_6_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'pid_correction_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_CORRECTION_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define PID_CORRECTION_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define PID_CORRECTION_PIO_7_COMPONENT_NAME pid_correction_pio_7
#define PID_CORRECTION_PIO_7_BASE 0xff222620
#define PID_CORRECTION_PIO_7_SPAN 16
#define PID_CORRECTION_PIO_7_END 0xff22262f
#define PID_CORRECTION_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PID_CORRECTION_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_CORRECTION_PIO_7_CAPTURE 0
#define PID_CORRECTION_PIO_7_DATA_WIDTH 32
#define PID_CORRECTION_PIO_7_DO_TEST_BENCH_WIRING 0
#define PID_CORRECTION_PIO_7_DRIVEN_SIM_VALUE 0
#define PID_CORRECTION_PIO_7_EDGE_TYPE NONE
#define PID_CORRECTION_PIO_7_FREQ 50000000
#define PID_CORRECTION_PIO_7_HAS_IN 1
#define PID_CORRECTION_PIO_7_HAS_OUT 0
#define PID_CORRECTION_PIO_7_HAS_TRI 0
#define PID_CORRECTION_PIO_7_IRQ_TYPE NONE
#define PID_CORRECTION_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'pid_values_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'PID_VALUES_PIO_'.
 * The prefix is the slave descriptor.
 */
#define PID_VALUES_PIO_COMPONENT_TYPE altera_avalon_pio
#define PID_VALUES_PIO_COMPONENT_NAME pid_values_pio
#define PID_VALUES_PIO_BASE 0xff222730
#define PID_VALUES_PIO_SPAN 16
#define PID_VALUES_PIO_END 0xff22273f
#define PID_VALUES_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define PID_VALUES_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PID_VALUES_PIO_CAPTURE 0
#define PID_VALUES_PIO_DATA_WIDTH 32
#define PID_VALUES_PIO_DO_TEST_BENCH_WIRING 0
#define PID_VALUES_PIO_DRIVEN_SIM_VALUE 0
#define PID_VALUES_PIO_EDGE_TYPE NONE
#define PID_VALUES_PIO_FREQ 50000000
#define PID_VALUES_PIO_HAS_IN 0
#define PID_VALUES_PIO_HAS_OUT 1
#define PID_VALUES_PIO_HAS_TRI 0
#define PID_VALUES_PIO_IRQ_TYPE NONE
#define PID_VALUES_PIO_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_0', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_0_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_0_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_0_COMPONENT_NAME pwm_pio_0
#define PWM_PIO_0_BASE 0xff222840
#define PWM_PIO_0_SPAN 16
#define PWM_PIO_0_END 0xff22284f
#define PWM_PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_0_CAPTURE 0
#define PWM_PIO_0_DATA_WIDTH 32
#define PWM_PIO_0_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_0_DRIVEN_SIM_VALUE 0
#define PWM_PIO_0_EDGE_TYPE NONE
#define PWM_PIO_0_FREQ 50000000
#define PWM_PIO_0_HAS_IN 0
#define PWM_PIO_0_HAS_OUT 1
#define PWM_PIO_0_HAS_TRI 0
#define PWM_PIO_0_IRQ_TYPE NONE
#define PWM_PIO_0_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_1', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_1_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_1_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_1_COMPONENT_NAME pwm_pio_1
#define PWM_PIO_1_BASE 0xff222950
#define PWM_PIO_1_SPAN 16
#define PWM_PIO_1_END 0xff22295f
#define PWM_PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_1_CAPTURE 0
#define PWM_PIO_1_DATA_WIDTH 32
#define PWM_PIO_1_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_1_DRIVEN_SIM_VALUE 0
#define PWM_PIO_1_EDGE_TYPE NONE
#define PWM_PIO_1_FREQ 50000000
#define PWM_PIO_1_HAS_IN 0
#define PWM_PIO_1_HAS_OUT 1
#define PWM_PIO_1_HAS_TRI 0
#define PWM_PIO_1_IRQ_TYPE NONE
#define PWM_PIO_1_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_2', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_2_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_2_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_2_COMPONENT_NAME pwm_pio_2
#define PWM_PIO_2_BASE 0xff223060
#define PWM_PIO_2_SPAN 16
#define PWM_PIO_2_END 0xff22306f
#define PWM_PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_2_CAPTURE 0
#define PWM_PIO_2_DATA_WIDTH 32
#define PWM_PIO_2_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_2_DRIVEN_SIM_VALUE 0
#define PWM_PIO_2_EDGE_TYPE NONE
#define PWM_PIO_2_FREQ 50000000
#define PWM_PIO_2_HAS_IN 0
#define PWM_PIO_2_HAS_OUT 1
#define PWM_PIO_2_HAS_TRI 0
#define PWM_PIO_2_IRQ_TYPE NONE
#define PWM_PIO_2_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_3', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_3_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_3_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_3_COMPONENT_NAME pwm_pio_3
#define PWM_PIO_3_BASE 0xff223170
#define PWM_PIO_3_SPAN 16
#define PWM_PIO_3_END 0xff22317f
#define PWM_PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_3_CAPTURE 0
#define PWM_PIO_3_DATA_WIDTH 32
#define PWM_PIO_3_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_3_DRIVEN_SIM_VALUE 0
#define PWM_PIO_3_EDGE_TYPE NONE
#define PWM_PIO_3_FREQ 50000000
#define PWM_PIO_3_HAS_IN 0
#define PWM_PIO_3_HAS_OUT 1
#define PWM_PIO_3_HAS_TRI 0
#define PWM_PIO_3_IRQ_TYPE NONE
#define PWM_PIO_3_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_4', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_4_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_4_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_4_COMPONENT_NAME pwm_pio_4
#define PWM_PIO_4_BASE 0xff223280
#define PWM_PIO_4_SPAN 16
#define PWM_PIO_4_END 0xff22328f
#define PWM_PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_4_CAPTURE 0
#define PWM_PIO_4_DATA_WIDTH 32
#define PWM_PIO_4_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_4_DRIVEN_SIM_VALUE 0
#define PWM_PIO_4_EDGE_TYPE NONE
#define PWM_PIO_4_FREQ 50000000
#define PWM_PIO_4_HAS_IN 0
#define PWM_PIO_4_HAS_OUT 1
#define PWM_PIO_4_HAS_TRI 0
#define PWM_PIO_4_IRQ_TYPE NONE
#define PWM_PIO_4_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_5', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_5_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_5_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_5_COMPONENT_NAME pwm_pio_5
#define PWM_PIO_5_BASE 0xff223390
#define PWM_PIO_5_SPAN 16
#define PWM_PIO_5_END 0xff22339f
#define PWM_PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_5_CAPTURE 0
#define PWM_PIO_5_DATA_WIDTH 32
#define PWM_PIO_5_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_5_DRIVEN_SIM_VALUE 0
#define PWM_PIO_5_EDGE_TYPE NONE
#define PWM_PIO_5_FREQ 50000000
#define PWM_PIO_5_HAS_IN 0
#define PWM_PIO_5_HAS_OUT 1
#define PWM_PIO_5_HAS_TRI 0
#define PWM_PIO_5_IRQ_TYPE NONE
#define PWM_PIO_5_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_6', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_6_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_6_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_6_COMPONENT_NAME pwm_pio_6
#define PWM_PIO_6_BASE 0xff223400
#define PWM_PIO_6_SPAN 16
#define PWM_PIO_6_END 0xff22340f
#define PWM_PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_6_CAPTURE 0
#define PWM_PIO_6_DATA_WIDTH 32
#define PWM_PIO_6_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_6_DRIVEN_SIM_VALUE 0
#define PWM_PIO_6_EDGE_TYPE NONE
#define PWM_PIO_6_FREQ 50000000
#define PWM_PIO_6_HAS_IN 0
#define PWM_PIO_6_HAS_OUT 1
#define PWM_PIO_6_HAS_TRI 0
#define PWM_PIO_6_IRQ_TYPE NONE
#define PWM_PIO_6_RESET_VALUE 0

/*
 * Macros for device 'pwm_pio_7', class 'altera_avalon_pio'
 * The macros are prefixed with 'PWM_PIO_7_'.
 * The prefix is the slave descriptor.
 */
#define PWM_PIO_7_COMPONENT_TYPE altera_avalon_pio
#define PWM_PIO_7_COMPONENT_NAME pwm_pio_7
#define PWM_PIO_7_BASE 0xff223510
#define PWM_PIO_7_SPAN 16
#define PWM_PIO_7_END 0xff22351f
#define PWM_PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PWM_PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PWM_PIO_7_CAPTURE 0
#define PWM_PIO_7_DATA_WIDTH 32
#define PWM_PIO_7_DO_TEST_BENCH_WIRING 0
#define PWM_PIO_7_DRIVEN_SIM_VALUE 0
#define PWM_PIO_7_EDGE_TYPE NONE
#define PWM_PIO_7_FREQ 50000000
#define PWM_PIO_7_HAS_IN 0
#define PWM_PIO_7_HAS_OUT 1
#define PWM_PIO_7_HAS_TRI 0
#define PWM_PIO_7_IRQ_TYPE NONE
#define PWM_PIO_7_RESET_VALUE 0

/*
 * Macros for device 'limit_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'LIMIT_PIO_'.
 * The prefix is the slave descriptor.
 */
#define LIMIT_PIO_COMPONENT_TYPE altera_avalon_pio
#define LIMIT_PIO_COMPONENT_NAME limit_pio
#define LIMIT_PIO_BASE 0xff223610
#define LIMIT_PIO_SPAN 16
#define LIMIT_PIO_END 0xff22361f
#define LIMIT_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LIMIT_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LIMIT_PIO_CAPTURE 0
#define LIMIT_PIO_DATA_WIDTH 8
#define LIMIT_PIO_DO_TEST_BENCH_WIRING 0
#define LIMIT_PIO_DRIVEN_SIM_VALUE 0
#define LIMIT_PIO_EDGE_TYPE NONE
#define LIMIT_PIO_FREQ 50000000
#define LIMIT_PIO_HAS_IN 1
#define LIMIT_PIO_HAS_OUT 0
#define LIMIT_PIO_HAS_TRI 0
#define LIMIT_PIO_IRQ_TYPE NONE
#define LIMIT_PIO_RESET_VALUE 0

/*
 * Macros for device 'heartbeat', class 'altera_avalon_pio'
 * The macros are prefixed with 'HEARTBEAT_'.
 * The prefix is the slave descriptor.
 */
#define HEARTBEAT_COMPONENT_TYPE altera_avalon_pio
#define HEARTBEAT_COMPONENT_NAME heartbeat
#define HEARTBEAT_BASE 0xff223710
#define HEARTBEAT_SPAN 16
#define HEARTBEAT_END 0xff22371f
#define HEARTBEAT_BIT_CLEARING_EDGE_REGISTER 0
#define HEARTBEAT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HEARTBEAT_CAPTURE 0
#define HEARTBEAT_DATA_WIDTH 32
#define HEARTBEAT_DO_TEST_BENCH_WIRING 0
#define HEARTBEAT_DRIVEN_SIM_VALUE 0
#define HEARTBEAT_EDGE_TYPE NONE
#define HEARTBEAT_FREQ 50000000
#define HEARTBEAT_HAS_IN 0
#define HEARTBEAT_HAS_OUT 1
#define HEARTBEAT_HAS_TRI 0
#define HEARTBEAT_IRQ_TYPE NONE
#define HEARTBEAT_RESET_VALUE 0

/*
 * Macros for device 'e_stop', class 'altera_avalon_pio'
 * The macros are prefixed with 'E_STOP_'.
 * The prefix is the slave descriptor.
 */
#define E_STOP_COMPONENT_TYPE altera_avalon_pio
#define E_STOP_COMPONENT_NAME e_stop
#define E_STOP_BASE 0xff223810
#define E_STOP_SPAN 16
#define E_STOP_END 0xff22381f
#define E_STOP_BIT_CLEARING_EDGE_REGISTER 0
#define E_STOP_BIT_MODIFYING_OUTPUT_REGISTER 0
#define E_STOP_CAPTURE 0
#define E_STOP_DATA_WIDTH 1
#define E_STOP_DO_TEST_BENCH_WIRING 0
#define E_STOP_DRIVEN_SIM_VALUE 0
#define E_STOP_EDGE_TYPE NONE
#define E_STOP_FREQ 50000000
#define E_STOP_HAS_IN 1
#define E_STOP_HAS_OUT 0
#define E_STOP_HAS_TRI 0
#define E_STOP_IRQ_TYPE NONE
#define E_STOP_RESET_VALUE 0

/*
 * Macros for device 'adc_0', class 'altera_up_avalon_adc'
 * The macros are prefixed with 'ADC_0_'.
 * The prefix is the slave descriptor.
 */
#define ADC_0_COMPONENT_TYPE altera_up_avalon_adc
#define ADC_0_COMPONENT_NAME adc_0
#define ADC_0_BASE 0xff223900
#define ADC_0_SPAN 32
#define ADC_0_END 0xff22391f

/*
 * Macros for device 'hps_0_gmac0', class 'stmmac'
 * The macros are prefixed with 'HPS_0_GMAC0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_GMAC0_COMPONENT_TYPE stmmac
#define HPS_0_GMAC0_COMPONENT_NAME hps_0_gmac0
#define HPS_0_GMAC0_BASE 0xff700000
#define HPS_0_GMAC0_SPAN 8192
#define HPS_0_GMAC0_END 0xff701fff

/*
 * Macros for device 'hps_0_gmac1', class 'stmmac'
 * The macros are prefixed with 'HPS_0_GMAC1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_GMAC1_COMPONENT_TYPE stmmac
#define HPS_0_GMAC1_COMPONENT_NAME hps_0_gmac1
#define HPS_0_GMAC1_BASE 0xff702000
#define HPS_0_GMAC1_SPAN 8192
#define HPS_0_GMAC1_END 0xff703fff

/*
 * Macros for device 'hps_0_sdmmc', class 'sdmmc'
 * The macros are prefixed with 'HPS_0_SDMMC_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_SDMMC_COMPONENT_TYPE sdmmc
#define HPS_0_SDMMC_COMPONENT_NAME hps_0_sdmmc
#define HPS_0_SDMMC_BASE 0xff704000
#define HPS_0_SDMMC_SPAN 4096
#define HPS_0_SDMMC_END 0xff704fff

/*
 * Macros for device 'hps_0_qspi', class 'cadence_qspi'
 * The macros are prefixed with 'HPS_0_QSPI_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_QSPI_COMPONENT_TYPE cadence_qspi
#define HPS_0_QSPI_COMPONENT_NAME hps_0_qspi
#define HPS_0_QSPI_BASE 0xff705000
#define HPS_0_QSPI_SPAN 256
#define HPS_0_QSPI_END 0xff7050ff

/*
 * Macros for device 'hps_0_fpgamgr', class 'altera_fpgamgr'
 * The macros are prefixed with 'HPS_0_FPGAMGR_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_FPGAMGR_COMPONENT_TYPE altera_fpgamgr
#define HPS_0_FPGAMGR_COMPONENT_NAME hps_0_fpgamgr
#define HPS_0_FPGAMGR_BASE 0xff706000
#define HPS_0_FPGAMGR_SPAN 4096
#define HPS_0_FPGAMGR_END 0xff706fff

/*
 * Macros for device 'hps_0_gpio0', class 'dw_gpio'
 * The macros are prefixed with 'HPS_0_GPIO0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_GPIO0_COMPONENT_TYPE dw_gpio
#define HPS_0_GPIO0_COMPONENT_NAME hps_0_gpio0
#define HPS_0_GPIO0_BASE 0xff708000
#define HPS_0_GPIO0_SPAN 256
#define HPS_0_GPIO0_END 0xff7080ff

/*
 * Macros for device 'hps_0_gpio1', class 'dw_gpio'
 * The macros are prefixed with 'HPS_0_GPIO1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_GPIO1_COMPONENT_TYPE dw_gpio
#define HPS_0_GPIO1_COMPONENT_NAME hps_0_gpio1
#define HPS_0_GPIO1_BASE 0xff709000
#define HPS_0_GPIO1_SPAN 256
#define HPS_0_GPIO1_END 0xff7090ff

/*
 * Macros for device 'hps_0_gpio2', class 'dw_gpio'
 * The macros are prefixed with 'HPS_0_GPIO2_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_GPIO2_COMPONENT_TYPE dw_gpio
#define HPS_0_GPIO2_COMPONENT_NAME hps_0_gpio2
#define HPS_0_GPIO2_BASE 0xff70a000
#define HPS_0_GPIO2_SPAN 256
#define HPS_0_GPIO2_END 0xff70a0ff

/*
 * Macros for device 'hps_0_l3regs', class 'altera_l3regs'
 * The macros are prefixed with 'HPS_0_L3REGS_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_L3REGS_COMPONENT_TYPE altera_l3regs
#define HPS_0_L3REGS_COMPONENT_NAME hps_0_l3regs
#define HPS_0_L3REGS_BASE 0xff800000
#define HPS_0_L3REGS_SPAN 4096
#define HPS_0_L3REGS_END 0xff800fff

/*
 * Macros for device 'hps_0_nand0', class 'denali_nand'
 * The macros are prefixed with 'HPS_0_NAND0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_NAND0_COMPONENT_TYPE denali_nand
#define HPS_0_NAND0_COMPONENT_NAME hps_0_nand0
#define HPS_0_NAND0_BASE 0xff900000
#define HPS_0_NAND0_SPAN 65536
#define HPS_0_NAND0_END 0xff90ffff

/*
 * Macros for device 'hps_0_usb0', class 'usb'
 * The macros are prefixed with 'HPS_0_USB0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_USB0_COMPONENT_TYPE usb
#define HPS_0_USB0_COMPONENT_NAME hps_0_usb0
#define HPS_0_USB0_BASE 0xffb00000
#define HPS_0_USB0_SPAN 262144
#define HPS_0_USB0_END 0xffb3ffff

/*
 * Macros for device 'hps_0_usb1', class 'usb'
 * The macros are prefixed with 'HPS_0_USB1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_USB1_COMPONENT_TYPE usb
#define HPS_0_USB1_COMPONENT_NAME hps_0_usb1
#define HPS_0_USB1_BASE 0xffb40000
#define HPS_0_USB1_SPAN 262144
#define HPS_0_USB1_END 0xffb7ffff

/*
 * Macros for device 'hps_0_dcan0', class 'bosch_dcan'
 * The macros are prefixed with 'HPS_0_DCAN0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_DCAN0_COMPONENT_TYPE bosch_dcan
#define HPS_0_DCAN0_COMPONENT_NAME hps_0_dcan0
#define HPS_0_DCAN0_BASE 0xffc00000
#define HPS_0_DCAN0_SPAN 4096
#define HPS_0_DCAN0_END 0xffc00fff

/*
 * Macros for device 'hps_0_dcan1', class 'bosch_dcan'
 * The macros are prefixed with 'HPS_0_DCAN1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_DCAN1_COMPONENT_TYPE bosch_dcan
#define HPS_0_DCAN1_COMPONENT_NAME hps_0_dcan1
#define HPS_0_DCAN1_BASE 0xffc01000
#define HPS_0_DCAN1_SPAN 4096
#define HPS_0_DCAN1_END 0xffc01fff

/*
 * Macros for device 'hps_0_uart0', class 'snps_uart'
 * The macros are prefixed with 'HPS_0_UART0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_UART0_COMPONENT_TYPE snps_uart
#define HPS_0_UART0_COMPONENT_NAME hps_0_uart0
#define HPS_0_UART0_BASE 0xffc02000
#define HPS_0_UART0_SPAN 256
#define HPS_0_UART0_END 0xffc020ff
#define HPS_0_UART0_FIFO_DEPTH 128
#define HPS_0_UART0_FIFO_HWFC 0
#define HPS_0_UART0_FIFO_MODE 1
#define HPS_0_UART0_FIFO_SWFC 0
#define HPS_0_UART0_FREQ 100000000

/*
 * Macros for device 'hps_0_uart1', class 'snps_uart'
 * The macros are prefixed with 'HPS_0_UART1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_UART1_COMPONENT_TYPE snps_uart
#define HPS_0_UART1_COMPONENT_NAME hps_0_uart1
#define HPS_0_UART1_BASE 0xffc03000
#define HPS_0_UART1_SPAN 256
#define HPS_0_UART1_END 0xffc030ff
#define HPS_0_UART1_FIFO_DEPTH 128
#define HPS_0_UART1_FIFO_HWFC 0
#define HPS_0_UART1_FIFO_MODE 1
#define HPS_0_UART1_FIFO_SWFC 0
#define HPS_0_UART1_FREQ 100000000

/*
 * Macros for device 'hps_0_i2c0', class 'designware_i2c'
 * The macros are prefixed with 'HPS_0_I2C0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_I2C0_COMPONENT_TYPE designware_i2c
#define HPS_0_I2C0_COMPONENT_NAME hps_0_i2c0
#define HPS_0_I2C0_BASE 0xffc04000
#define HPS_0_I2C0_SPAN 256
#define HPS_0_I2C0_END 0xffc040ff

/*
 * Macros for device 'hps_0_i2c1', class 'designware_i2c'
 * The macros are prefixed with 'HPS_0_I2C1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_I2C1_COMPONENT_TYPE designware_i2c
#define HPS_0_I2C1_COMPONENT_NAME hps_0_i2c1
#define HPS_0_I2C1_BASE 0xffc05000
#define HPS_0_I2C1_SPAN 256
#define HPS_0_I2C1_END 0xffc050ff

/*
 * Macros for device 'hps_0_i2c2', class 'designware_i2c'
 * The macros are prefixed with 'HPS_0_I2C2_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_I2C2_COMPONENT_TYPE designware_i2c
#define HPS_0_I2C2_COMPONENT_NAME hps_0_i2c2
#define HPS_0_I2C2_BASE 0xffc06000
#define HPS_0_I2C2_SPAN 256
#define HPS_0_I2C2_END 0xffc060ff

/*
 * Macros for device 'hps_0_i2c3', class 'designware_i2c'
 * The macros are prefixed with 'HPS_0_I2C3_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_I2C3_COMPONENT_TYPE designware_i2c
#define HPS_0_I2C3_COMPONENT_NAME hps_0_i2c3
#define HPS_0_I2C3_BASE 0xffc07000
#define HPS_0_I2C3_SPAN 256
#define HPS_0_I2C3_END 0xffc070ff

/*
 * Macros for device 'hps_0_timer0', class 'dw_apb_timer_sp'
 * The macros are prefixed with 'HPS_0_TIMER0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_TIMER0_COMPONENT_TYPE dw_apb_timer_sp
#define HPS_0_TIMER0_COMPONENT_NAME hps_0_timer0
#define HPS_0_TIMER0_BASE 0xffc08000
#define HPS_0_TIMER0_SPAN 256
#define HPS_0_TIMER0_END 0xffc080ff

/*
 * Macros for device 'hps_0_timer1', class 'dw_apb_timer_sp'
 * The macros are prefixed with 'HPS_0_TIMER1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_TIMER1_COMPONENT_TYPE dw_apb_timer_sp
#define HPS_0_TIMER1_COMPONENT_NAME hps_0_timer1
#define HPS_0_TIMER1_BASE 0xffc09000
#define HPS_0_TIMER1_SPAN 256
#define HPS_0_TIMER1_END 0xffc090ff

/*
 * Macros for device 'hps_0_sdrctl', class 'altera_sdrctl'
 * The macros are prefixed with 'HPS_0_SDRCTL_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_SDRCTL_COMPONENT_TYPE altera_sdrctl
#define HPS_0_SDRCTL_COMPONENT_NAME hps_0_sdrctl
#define HPS_0_SDRCTL_BASE 0xffc25000
#define HPS_0_SDRCTL_SPAN 4096
#define HPS_0_SDRCTL_END 0xffc25fff

/*
 * Macros for device 'hps_0_timer2', class 'dw_apb_timer_osc'
 * The macros are prefixed with 'HPS_0_TIMER2_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_TIMER2_COMPONENT_TYPE dw_apb_timer_osc
#define HPS_0_TIMER2_COMPONENT_NAME hps_0_timer2
#define HPS_0_TIMER2_BASE 0xffd00000
#define HPS_0_TIMER2_SPAN 256
#define HPS_0_TIMER2_END 0xffd000ff

/*
 * Macros for device 'hps_0_timer3', class 'dw_apb_timer_osc'
 * The macros are prefixed with 'HPS_0_TIMER3_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_TIMER3_COMPONENT_TYPE dw_apb_timer_osc
#define HPS_0_TIMER3_COMPONENT_NAME hps_0_timer3
#define HPS_0_TIMER3_BASE 0xffd01000
#define HPS_0_TIMER3_SPAN 256
#define HPS_0_TIMER3_END 0xffd010ff

/*
 * Macros for device 'hps_0_wd_timer0', class 'dw_wd_timer'
 * The macros are prefixed with 'HPS_0_WD_TIMER0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_WD_TIMER0_COMPONENT_TYPE dw_wd_timer
#define HPS_0_WD_TIMER0_COMPONENT_NAME hps_0_wd_timer0
#define HPS_0_WD_TIMER0_BASE 0xffd02000
#define HPS_0_WD_TIMER0_SPAN 256
#define HPS_0_WD_TIMER0_END 0xffd020ff

/*
 * Macros for device 'hps_0_wd_timer1', class 'dw_wd_timer'
 * The macros are prefixed with 'HPS_0_WD_TIMER1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_WD_TIMER1_COMPONENT_TYPE dw_wd_timer
#define HPS_0_WD_TIMER1_COMPONENT_NAME hps_0_wd_timer1
#define HPS_0_WD_TIMER1_BASE 0xffd03000
#define HPS_0_WD_TIMER1_SPAN 256
#define HPS_0_WD_TIMER1_END 0xffd030ff

/*
 * Macros for device 'hps_0_clkmgr', class 'asimov_clkmgr'
 * The macros are prefixed with 'HPS_0_CLKMGR_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_CLKMGR_COMPONENT_TYPE asimov_clkmgr
#define HPS_0_CLKMGR_COMPONENT_NAME hps_0_clkmgr
#define HPS_0_CLKMGR_BASE 0xffd04000
#define HPS_0_CLKMGR_SPAN 4096
#define HPS_0_CLKMGR_END 0xffd04fff

/*
 * Macros for device 'hps_0_rstmgr', class 'altera_rstmgr'
 * The macros are prefixed with 'HPS_0_RSTMGR_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_RSTMGR_COMPONENT_TYPE altera_rstmgr
#define HPS_0_RSTMGR_COMPONENT_NAME hps_0_rstmgr
#define HPS_0_RSTMGR_BASE 0xffd05000
#define HPS_0_RSTMGR_SPAN 256
#define HPS_0_RSTMGR_END 0xffd050ff

/*
 * Macros for device 'hps_0_sysmgr', class 'altera_sysmgr'
 * The macros are prefixed with 'HPS_0_SYSMGR_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_SYSMGR_COMPONENT_TYPE altera_sysmgr
#define HPS_0_SYSMGR_COMPONENT_NAME hps_0_sysmgr
#define HPS_0_SYSMGR_BASE 0xffd08000
#define HPS_0_SYSMGR_SPAN 1024
#define HPS_0_SYSMGR_END 0xffd083ff

/*
 * Macros for device 'hps_0_dma', class 'arm_pl330_dma'
 * The macros are prefixed with 'HPS_0_DMA_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_DMA_COMPONENT_TYPE arm_pl330_dma
#define HPS_0_DMA_COMPONENT_NAME hps_0_dma
#define HPS_0_DMA_BASE 0xffe01000
#define HPS_0_DMA_SPAN 4096
#define HPS_0_DMA_END 0xffe01fff

/*
 * Macros for device 'hps_0_spim0', class 'spi'
 * The macros are prefixed with 'HPS_0_SPIM0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_SPIM0_COMPONENT_TYPE spi
#define HPS_0_SPIM0_COMPONENT_NAME hps_0_spim0
#define HPS_0_SPIM0_BASE 0xfff00000
#define HPS_0_SPIM0_SPAN 256
#define HPS_0_SPIM0_END 0xfff000ff

/*
 * Macros for device 'hps_0_spim1', class 'spi'
 * The macros are prefixed with 'HPS_0_SPIM1_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_SPIM1_COMPONENT_TYPE spi
#define HPS_0_SPIM1_COMPONENT_NAME hps_0_spim1
#define HPS_0_SPIM1_BASE 0xfff01000
#define HPS_0_SPIM1_SPAN 256
#define HPS_0_SPIM1_END 0xfff010ff

/*
 * Macros for device 'hps_0_scu', class 'scu'
 * The macros are prefixed with 'HPS_0_SCU_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_SCU_COMPONENT_TYPE scu
#define HPS_0_SCU_COMPONENT_NAME hps_0_scu
#define HPS_0_SCU_BASE 0xfffec000
#define HPS_0_SCU_SPAN 256
#define HPS_0_SCU_END 0xfffec0ff

/*
 * Macros for device 'hps_0_timer', class 'arm_internal_timer'
 * The macros are prefixed with 'HPS_0_TIMER_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_TIMER_COMPONENT_TYPE arm_internal_timer
#define HPS_0_TIMER_COMPONENT_NAME hps_0_timer
#define HPS_0_TIMER_BASE 0xfffec600
#define HPS_0_TIMER_SPAN 256
#define HPS_0_TIMER_END 0xfffec6ff

/*
 * Macros for device 'hps_0_arm_gic_0', class 'arm_gic'
 * The macros are prefixed with 'HPS_0_ARM_GIC_0_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_ARM_GIC_0_COMPONENT_TYPE arm_gic
#define HPS_0_ARM_GIC_0_COMPONENT_NAME hps_0_arm_gic_0
#define HPS_0_ARM_GIC_0_BASE 0xfffed000
#define HPS_0_ARM_GIC_0_SPAN 4096
#define HPS_0_ARM_GIC_0_END 0xfffedfff

/*
 * Macros for device 'hps_0_L2', class 'arm_pl310_L2'
 * The macros are prefixed with 'HPS_0_L2_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_L2_COMPONENT_TYPE arm_pl310_L2
#define HPS_0_L2_COMPONENT_NAME hps_0_L2
#define HPS_0_L2_BASE 0xfffef000
#define HPS_0_L2_SPAN 4096
#define HPS_0_L2_END 0xfffeffff

/*
 * Macros for device 'hps_0_axi_ocram', class 'axi_ocram'
 * The macros are prefixed with 'HPS_0_AXI_OCRAM_'.
 * The prefix is the slave descriptor.
 */
#define HPS_0_AXI_OCRAM_COMPONENT_TYPE axi_ocram
#define HPS_0_AXI_OCRAM_COMPONENT_NAME hps_0_axi_ocram
#define HPS_0_AXI_OCRAM_BASE 0xffff0000
#define HPS_0_AXI_OCRAM_SPAN 65536
#define HPS_0_AXI_OCRAM_END 0xffffffff
#define HPS_0_AXI_OCRAM_SIZE_MULTIPLE 1
#define HPS_0_AXI_OCRAM_SIZE_VALUE 1<<16
#define HPS_0_AXI_OCRAM_WRITABLE 1
#define HPS_0_AXI_OCRAM_MEMORY_INFO_GENERATE_DAT_SYM 0
#define HPS_0_AXI_OCRAM_MEMORY_INFO_GENERATE_HEX 0
#define HPS_0_AXI_OCRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 16


#endif /* _ALTERA_HPS_0_ARM_A9_1_H_ */