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top_cache_axi: Rebuild for updated core;
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- Fix combo loop if MMU present.
- Improve AXI4 protocol compliance.

Test: Boots Linux.
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@ultraembedded
ultraembedded committed May 3, 2020
1 parent 480d6d9 commit c17cfba
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Showing 3 changed files with 97 additions and 68 deletions.
4 changes: 3 additions & 1 deletion top_cache_axi/src_v/dcache.v
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Original file line number Diff line number Diff line change
Expand Up @@ -197,7 +197,9 @@ dcache_pmem_mux
u_pmem_mux
(
// Inputs
.outport_accept_i(pmem_accept_w)
.clk_i(clk_i)
,.rst_i(rst_i)
,.outport_accept_i(pmem_accept_w)
,.outport_ack_i(pmem_ack_w)
,.outport_error_i(pmem_error_w)
,.outport_read_data_i(pmem_read_data_w)
Expand Down
141 changes: 79 additions & 62 deletions top_cache_axi/src_v/dcache_axi_axi.v
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Original file line number Diff line number Diff line change
Expand Up @@ -99,36 +99,6 @@ module dcache_axi_axi



//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
reg awvalid_inhibit_q;
reg wvalid_inhibit_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
awvalid_inhibit_q <= 1'b0;
else if (outport_awvalid_o && outport_awready_i && outport_wvalid_o && !outport_wready_i)
awvalid_inhibit_q <= 1'b1;
else if (outport_awvalid_o && outport_awready_i && outport_awlen_o != 8'b0)
awvalid_inhibit_q <= 1'b1;
else if (outport_wvalid_o && outport_wready_i && outport_wlast_o)
awvalid_inhibit_q <= 1'b0;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wvalid_inhibit_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i && outport_awvalid_o && !outport_awready_i)
wvalid_inhibit_q <= 1'b1;
else if (outport_awvalid_o && outport_awready_i)
wvalid_inhibit_q <= 1'b0;

assign outport_awvalid_o = (inport_valid_i & inport_write_i & ~awvalid_inhibit_q);
assign outport_awaddr_o = inport_addr_i;
assign outport_awid_o = inport_id_i;
assign outport_awlen_o = inport_len_i;
assign outport_awburst_o = inport_burst_i;

//-------------------------------------------------------------
// Write burst tracking
//-------------------------------------------------------------
Expand All @@ -137,43 +107,89 @@ reg [7:0] req_cnt_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
req_cnt_q <= 8'b0;
else if (outport_awvalid_o && outport_awready_i)
else if (inport_valid_i && inport_write_i && inport_accept_o)
begin
// First data not accepted yet
if (!outport_wready_i && !wvalid_inhibit_q)
req_cnt_q <= (outport_awlen_o + 8'd1);
// First data already accepted
if (req_cnt_q != 8'b0)
req_cnt_q <= req_cnt_q - 8'd1;
else
req_cnt_q <= outport_awlen_o;
req_cnt_q <= inport_len_i;
end
else if (req_cnt_q != 8'd0 && outport_wvalid_o && outport_wready_i)
req_cnt_q <= req_cnt_q - 8'd1;

wire wlast_w = (outport_awvalid_o && outport_awlen_o == 8'b0) || (req_cnt_q == 8'd1);

//-------------------------------------------------------------
// Write data skid buffer
// Request skid buffer
//-------------------------------------------------------------
reg buf_valid_q;
reg valid_q;
reg [83:0] buf_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
buf_valid_q <= 1'b0;
else if (outport_wvalid_o && !outport_wready_i && outport_awvalid_o && outport_awready_i)
buf_valid_q <= 1'b1;
else if (outport_wready_i)
buf_valid_q <= 1'b0;
valid_q <= 1'b0;
else if (inport_valid_i && inport_accept_o && ((outport_awvalid_o && !outport_awready_i) || (outport_wvalid_o && !outport_wready_i) || (outport_arvalid_o && !outport_arready_i)))
valid_q <= 1'b1;
else if ((!outport_awvalid_o || outport_awready_i) && (!outport_wvalid_o || outport_wready_i) && (!outport_arvalid_o || outport_arready_i))
valid_q <= 1'b0;

wire inport_valid_w = valid_q || inport_valid_i;
wire inport_write_w = valid_q ? buf_q[0:0] : inport_write_i;
wire [ 31:0] inport_addr_w = valid_q ? buf_q[32:1] : inport_addr_i;
wire [ 3:0] inport_id_w = valid_q ? buf_q[36:33] : inport_id_i;
wire [ 7:0] inport_len_w = valid_q ? buf_q[44:37] : inport_len_i;
wire [ 1:0] inport_burst_w = valid_q ? buf_q[46:45] : inport_burst_i;
wire [ 31:0] inport_wdata_w = valid_q ? buf_q[78:47] : inport_wdata_i;
wire [ 3:0] inport_wstrb_w = valid_q ? buf_q[82:79] : inport_wstrb_i;
wire inport_wlast_w = valid_q ? buf_q[83:83] : (inport_len_i == 8'd0 && req_cnt_q == 8'd0) || (req_cnt_q == 8'd1);

reg [36:0] buf_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
buf_q <= 37'b0;
buf_q <= 84'b0;
else
buf_q <= {outport_wlast_o, outport_wstrb_o, outport_wdata_o};
buf_q <= {inport_wlast_w, inport_wstrb_w, inport_wdata_w, inport_burst_w, inport_len_w, inport_id_w, inport_addr_w, inport_write_w};

wire skid_busy_w = valid_q;

//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
reg awvalid_q;
reg wvalid_q;
reg wlast_q;

wire wr_cmd_accepted_w = (outport_awvalid_o && outport_awready_i) || awvalid_q;
wire wr_data_accepted_w = (outport_wvalid_o && outport_wready_i) || wvalid_q;
wire wr_data_last_w = (wvalid_q & wlast_q) || (outport_wvalid_o && outport_wready_i && outport_wlast_o);

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
awvalid_q <= 1'b0;
else if (outport_awvalid_o && outport_awready_i && (!wr_data_accepted_w || !wr_data_last_w))
awvalid_q <= 1'b1;
else if (wr_data_accepted_w && wr_data_last_w)
awvalid_q <= 1'b0;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wvalid_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wlast_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i)
wlast_q <= outport_wlast_o;

assign outport_awvalid_o = (inport_valid_w & inport_write_w & ~awvalid_q);
assign outport_awaddr_o = inport_addr_w;
assign outport_awid_o = inport_id_w;
assign outport_awlen_o = inport_len_w;
assign outport_awburst_o = inport_burst_w;

assign outport_wvalid_o = buf_valid_q ? 1'b1 : (inport_valid_i & inport_write_i & ~wvalid_inhibit_q);
assign outport_wdata_o = buf_valid_q ? buf_q[31:0] : inport_wdata_i;
assign outport_wstrb_o = buf_valid_q ? buf_q[35:32] : inport_wstrb_i;
assign outport_wlast_o = buf_valid_q ? buf_q[36:36] : wlast_w;
assign outport_wvalid_o = (inport_valid_w & inport_write_w & ~wvalid_q);
assign outport_wdata_o = inport_wdata_w;
assign outport_wstrb_o = inport_wstrb_w;
assign outport_wlast_o = inport_wlast_w;

assign inport_bvalid_o = outport_bvalid_i;
assign inport_bresp_o = outport_bresp_i;
Expand All @@ -183,11 +199,11 @@ assign outport_bready_o = inport_bready_i;
//-------------------------------------------------------------
// Read Request
//-------------------------------------------------------------
assign outport_arvalid_o = inport_valid_i & ~inport_write_i;
assign outport_araddr_o = inport_addr_i;
assign outport_arid_o = inport_id_i;
assign outport_arlen_o = inport_len_i;
assign outport_arburst_o = inport_burst_i;
assign outport_arvalid_o = inport_valid_w & ~inport_write_w;
assign outport_araddr_o = inport_addr_w;
assign outport_arid_o = inport_id_w;
assign outport_arlen_o = inport_len_w;
assign outport_arburst_o = inport_burst_w;
assign outport_rready_o = inport_rready_i;

assign inport_rvalid_o = outport_rvalid_i;
Expand All @@ -199,9 +215,10 @@ assign inport_rlast_o = outport_rlast_i;
//-------------------------------------------------------------
// Accept logic
//-------------------------------------------------------------
assign inport_accept_o = (outport_awvalid_o && outport_awready_i) ||
(outport_wvalid_o && outport_wready_i && !buf_valid_q) ||
(outport_arvalid_o && outport_arready_i);
assign inport_accept_o = !skid_busy_w &&
((outport_awvalid_o && outport_awready_i) ||
(outport_wvalid_o && outport_wready_i) ||
(outport_arvalid_o && outport_arready_i));


endmodule
20 changes: 15 additions & 5 deletions top_cache_axi/src_v/dcache_pmem_mux.v
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,9 @@
module dcache_pmem_mux
(
// Inputs
input outport_accept_i
input clk_i
,input rst_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
Expand Down Expand Up @@ -88,6 +90,7 @@ reg outport_rd_r;
reg [ 7:0] outport_len_r;
reg [ 31:0] outport_addr_r;
reg [ 31:0] outport_write_data_r;
reg select_q;

always @ *
begin
Expand Down Expand Up @@ -117,12 +120,19 @@ assign outport_len_o = outport_len_r;
assign outport_addr_o = outport_addr_r;
assign outport_write_data_o = outport_write_data_r;

assign inport0_ack_o = (select_i == 1'd0) && outport_ack_i;
assign inport0_error_o = (select_i == 1'd0) && outport_error_i;
// Delayed version of selector to match phase of response signals
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
select_q <= 1'b0;
else
select_q <= select_i;

assign inport0_ack_o = (select_q == 1'd0) && outport_ack_i;
assign inport0_error_o = (select_q == 1'd0) && outport_error_i;
assign inport0_read_data_o = outport_read_data_i;
assign inport0_accept_o = (select_i == 1'd0) && outport_accept_i;
assign inport1_ack_o = (select_i == 1'd1) && outport_ack_i;
assign inport1_error_o = (select_i == 1'd1) && outport_error_i;
assign inport1_ack_o = (select_q == 1'd1) && outport_ack_i;
assign inport1_error_o = (select_q == 1'd1) && outport_error_i;
assign inport1_read_data_o = outport_read_data_i;
assign inport1_accept_o = (select_i == 1'd1) && outport_accept_i;

Expand Down

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