Add CSR_SIM_CTRL alias for CSR_SCRATCH. Minor change to allow core to…

… run same SW as biRISC-V
ultraembedded · Mar 14, 2020 · c3ce172 · c3ce172
1 parent 2a8cd88
commit c3ce172
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Showing 8 changed files with 12 additions and 3 deletions.
diff --git a/core/rv32i/riscv_csr.v b/core/rv32i/riscv_csr.v
@@ -539,7 +539,7 @@ begin
 
 `ifdef verilator
     // CSR SIM_CTRL
-    if (opcode_valid_i && (set_r || clr_r) && (imm12_r[11:0] == `CSR_DSCRATCH) && !csr_access_fault_w)
+    if (opcode_valid_i && (set_r || clr_r) && (imm12_r[11:0] == `CSR_DSCRATCH || imm12_r[11:0] == `CSR_SIM_CTRL) && !csr_access_fault_w)
     begin
         case (data_r & 32'hFF000000)
         `CSR_SIM_CTRL_EXIT:

diff --git a/core/rv32i/riscv_defs.v b/core/rv32i/riscv_defs.v
@@ -394,6 +394,8 @@
 //--------------------------------------------------------------------
 `define CSR_DSCRATCH       12'h7b2
 `define CSR_DSCRATCH_MASK  32'hFFFFFFFF
+`define CSR_SIM_CTRL       12'h8b2
+`define CSR_SIM_CTRL_MASK  32'hFFFFFFFF
     `define CSR_SIM_CTRL_EXIT (0 << 24)
     `define CSR_SIM_CTRL_PUTC (1 << 24)
     `define CSR_SIM_CTRL_GETC (2 << 24)

diff --git a/core/rv32i_spartan6/riscv_csr.v b/core/rv32i_spartan6/riscv_csr.v
@@ -539,7 +539,7 @@ begin
 
 `ifdef verilator
     // CSR SIM_CTRL
-    if (opcode_valid_i && (set_r || clr_r) && (imm12_r[11:0] == `CSR_DSCRATCH) && !csr_access_fault_w)
+    if (opcode_valid_i && (set_r || clr_r) && (imm12_r[11:0] == `CSR_DSCRATCH || imm12_r[11:0] == `CSR_SIM_CTRL) && !csr_access_fault_w)
     begin
         case (data_r & 32'hFF000000)
         `CSR_SIM_CTRL_EXIT:

diff --git a/core/rv32i_spartan6/riscv_defs.v b/core/rv32i_spartan6/riscv_defs.v
@@ -394,6 +394,8 @@
 //--------------------------------------------------------------------
 `define CSR_DSCRATCH       12'h7b2
 `define CSR_DSCRATCH_MASK  32'hFFFFFFFF
+`define CSR_SIM_CTRL       12'h8b2
+`define CSR_SIM_CTRL_MASK  32'hFFFFFFFF
     `define CSR_SIM_CTRL_EXIT (0 << 24)
     `define CSR_SIM_CTRL_PUTC (1 << 24)
     `define CSR_SIM_CTRL_GETC (2 << 24)

diff --git a/core/rv32im/riscv_csr.v b/core/rv32im/riscv_csr.v
@@ -540,7 +540,7 @@ begin
 
 `ifdef verilator
     // CSR SIM_CTRL
-    if (opcode_valid_i && (set_r || clr_r) && (imm12_r[11:0] == `CSR_DSCRATCH) && !csr_access_fault_w)
+    if (opcode_valid_i && (set_r || clr_r) && (imm12_r[11:0] == `CSR_DSCRATCH || imm12_r[11:0] == `CSR_SIM_CTRL) && !csr_access_fault_w)
     begin
         case (data_r & 32'hFF000000)
         `CSR_SIM_CTRL_EXIT:

diff --git a/core/rv32im/riscv_defs.v b/core/rv32im/riscv_defs.v
@@ -394,6 +394,8 @@
 //--------------------------------------------------------------------
 `define CSR_DSCRATCH       12'h7b2
 `define CSR_DSCRATCH_MASK  32'hFFFFFFFF
+`define CSR_SIM_CTRL       12'h8b2
+`define CSR_SIM_CTRL_MASK  32'hFFFFFFFF
     `define CSR_SIM_CTRL_EXIT (0 << 24)
     `define CSR_SIM_CTRL_PUTC (1 << 24)
     `define CSR_SIM_CTRL_GETC (2 << 24)

diff --git a/isa_sim/riscv.cpp b/isa_sim/riscv.cpp
@@ -686,6 +686,7 @@ uint32_t Riscv::access_csr(uint32_t address, uint32_t data, bool set, bool clr)
         // Simulation control
         //--------------------------------------------------------
         case CSR_DSCRATCH:
+        case CSR_SIM_CTRL:
             switch (data & 0xFF000000)
             {
                 case CSR_SIM_CTRL_EXIT:

diff --git a/isa_sim/riscv_isa.h b/isa_sim/riscv_isa.h
@@ -510,6 +510,8 @@ static const char * inst_names[ENUM_INST_MAX+1] =
 //--------------------------------------------------------------------
 #define CSR_DSCRATCH       0x7b2
 #define CSR_DSCRATCH_MASK  0xFFFFFFFF
+#define CSR_SIM_CTRL       0x8b2
+#define CSR_SIM_CTRL_MASK  0xFFFFFFFF
     #define CSR_SIM_CTRL_EXIT  (0 << 24)
     #define CSR_SIM_CTRL_PUTC  (1 << 24)
     #define CSR_SIM_CTRL_GETC  (2 << 24)