V0.9.8: Add cache writeback control. Add top level params for cacheab…

…le addresses.
ultraembedded · Sep 21, 2019 · f544799 · f544799
1 parent 9a4ff4a
commit f544799
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diff --git a/core/rv32i/riscv_alu.v b/core/rv32i/riscv_alu.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i/riscv_core.v b/core/rv32i/riscv_core.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //
@@ -40,6 +40,16 @@
 //-----------------------------------------------------------------
 
 module riscv_core
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+     parameter MEM_CACHE_ADDR_MIN = 0
+    ,parameter MEM_CACHE_ADDR_MAX = 32'h7fffffff
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
 (
     // Inputs
      input           clk_i
@@ -65,6 +75,7 @@ module riscv_core
     ,output          mem_d_cacheable_o
     ,output [ 10:0]  mem_d_req_tag_o
     ,output          mem_d_invalidate_o
+    ,output          mem_d_writeback_o
     ,output          mem_d_flush_o
     ,output          mem_i_rd_o
     ,output          mem_i_flush_o
@@ -115,7 +126,8 @@ wire           writeback_exec_squash_w;
 wire  [ 31:0]  opcode_ra_operand_w;
 
 
-riscv_csr u_csr
+riscv_csr
+u_csr
 (
     // Inputs
      .clk_i(clk_i)
@@ -152,7 +164,12 @@ riscv_csr u_csr
 );
 
 
-riscv_lsu u_lsu
+riscv_lsu
+#(
+     .MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
+    ,.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
+)
+u_lsu
 (
     // Inputs
      .clk_i(clk_i)
@@ -180,6 +197,7 @@ riscv_lsu u_lsu
     ,.mem_cacheable_o(mem_d_cacheable_o)
     ,.mem_req_tag_o(mem_d_req_tag_o)
     ,.mem_invalidate_o(mem_d_invalidate_o)
+    ,.mem_writeback_o(mem_d_writeback_o)
     ,.mem_flush_o(mem_d_flush_o)
     ,.writeback_idx_o(writeback_mem_idx_w)
     ,.writeback_squash_o(writeback_mem_squash_w)
@@ -195,7 +213,8 @@ riscv_lsu u_lsu
 );
 
 
-riscv_exec u_exec
+riscv_exec
+u_exec
 (
     // Inputs
      .clk_i(clk_i)
@@ -220,7 +239,8 @@ riscv_exec u_exec
 );
 
 
-riscv_decode u_decode
+riscv_decode
+u_decode
 (
     // Inputs
      .clk_i(clk_i)
@@ -269,7 +289,8 @@ riscv_decode u_decode
 );
 
 
-riscv_fetch u_fetch
+riscv_fetch
+u_fetch
 (
     // Inputs
      .clk_i(clk_i)

diff --git a/core/rv32i/riscv_csr.v b/core/rv32i/riscv_csr.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i/riscv_decode.v b/core/rv32i/riscv_decode.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //
@@ -444,7 +444,7 @@ function set_register; /*verilator public*/
     input [4:0] r;
     input [31:0] value;
 begin
-    u_regfile.set_register(r,value);
+    set_register = u_regfile.set_register(r,value);
 end
 endfunction
 `endif

diff --git a/core/rv32i/riscv_defs.v b/core/rv32i/riscv_defs.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i/riscv_exec.v b/core/rv32i/riscv_exec.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i/riscv_fetch.v b/core/rv32i/riscv_fetch.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i/riscv_lsu.v b/core/rv32i/riscv_lsu.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //
@@ -40,6 +40,16 @@
 //-----------------------------------------------------------------
 
 module riscv_lsu
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+     parameter MEM_CACHE_ADDR_MIN = 0
+    ,parameter MEM_CACHE_ADDR_MAX = 32'h7fffffff
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
 (
     // Inputs
      input           clk_i
@@ -67,6 +77,7 @@ module riscv_lsu
     ,output          mem_cacheable_o
     ,output [ 10:0]  mem_req_tag_o
     ,output          mem_invalidate_o
+    ,output          mem_writeback_o
     ,output          mem_flush_o
     ,output [  4:0]  writeback_idx_o
     ,output          writeback_squash_o
@@ -98,6 +109,7 @@ reg [  3:0]  mem_wr_q;
 reg          mem_cacheable_q;
 reg [ 10:0]  mem_req_tag_q;
 reg          mem_invalidate_q;
+reg          mem_writeback_q;
 reg          mem_flush_q;
 reg          mem_unaligned_ld_q;
 reg          mem_unaligned_st_q;
@@ -157,11 +169,12 @@ begin
     mem_req_tag_q      <= 11'b0;
     mem_cacheable_q    <= 1'b0;
     mem_invalidate_q   <= 1'b0;
+    mem_writeback_q    <= 1'b0;
     mem_flush_q        <= 1'b0;
     mem_unaligned_ld_q <= 1'b0;
     mem_unaligned_st_q <= 1'b0;
 end
-else if (!((mem_invalidate_o || mem_flush_o || mem_rd_o || mem_wr_o != 4'b0) && !mem_accept_i))
+else if (!((mem_writeback_o || mem_invalidate_o || mem_flush_o || mem_rd_o || mem_wr_o != 4'b0) && !mem_accept_i))
 begin
     mem_addr_q         <= 32'b0;
     mem_data_wr_q      <= 32'b0;
@@ -170,6 +183,7 @@ begin
     mem_cacheable_q    <= 1'b0;
     mem_req_tag_q      <= 11'b0;
     mem_invalidate_q   <= 1'b0;
+    mem_writeback_q    <= 1'b0;
     mem_flush_q        <= 1'b0;
     mem_unaligned_ld_q <=  load_inst_w & mem_unaligned_r;
     mem_unaligned_st_q <= ~load_inst_w & mem_unaligned_r;
@@ -236,11 +250,13 @@ begin
 
 /* verilator lint_off UNSIGNED */
 /* verilator lint_off CMPCONST */
-    mem_cacheable_q  <= mem_addr_r >= 32'h0 && mem_addr_r <= 32'h7fffffff;
+    mem_cacheable_q  <= (mem_addr_r >= MEM_CACHE_ADDR_MIN && mem_addr_r <= MEM_CACHE_ADDR_MAX) ||
+                        (opcode_valid_i && (dcache_invalidate_w || dcache_writeback_w || dcache_flush_w));
 /* verilator lint_on CMPCONST */
 /* verilator lint_on UNSIGNED */
 
     mem_invalidate_q <= opcode_valid_i & dcache_invalidate_w;
+    mem_writeback_q  <= opcode_valid_i & dcache_writeback_w;
     mem_flush_q      <= opcode_valid_i & dcache_flush_w;
     mem_addr_q       <= mem_addr_r;
 end
@@ -252,10 +268,11 @@ assign mem_wr_o         = mem_wr_q;
 assign mem_cacheable_o  = mem_cacheable_q;
 assign mem_req_tag_o    = mem_req_tag_q;
 assign mem_invalidate_o = mem_invalidate_q;
+assign mem_writeback_o  = mem_writeback_q;
 assign mem_flush_o      = mem_flush_q;
 
 // Stall upstream if cache is busy
-assign stall_o          = ((mem_invalidate_o || mem_flush_o || mem_rd_o || mem_wr_o != 4'b0) && !mem_accept_i);
+assign stall_o          = ((mem_writeback_o || mem_invalidate_o || mem_flush_o || mem_rd_o || mem_wr_o != 4'b0) && !mem_accept_i);
 
 //-----------------------------------------------------------------
 // Error handling / faults

diff --git a/core/rv32i/riscv_regfile.v b/core/rv32i/riscv_regfile.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i_spartan6/riscv_alu.v b/core/rv32i_spartan6/riscv_alu.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i_spartan6/riscv_core.v b/core/rv32i_spartan6/riscv_core.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //
@@ -40,6 +40,16 @@
 //-----------------------------------------------------------------
 
 module riscv_core
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+     parameter MEM_CACHE_ADDR_MIN = 0
+    ,parameter MEM_CACHE_ADDR_MAX = 32'h7fffffff
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
 (
     // Inputs
      input           clk_i
@@ -65,6 +75,7 @@ module riscv_core
     ,output          mem_d_cacheable_o
     ,output [ 10:0]  mem_d_req_tag_o
     ,output          mem_d_invalidate_o
+    ,output          mem_d_writeback_o
     ,output          mem_d_flush_o
     ,output          mem_i_rd_o
     ,output          mem_i_flush_o
@@ -115,7 +126,8 @@ wire           writeback_exec_squash_w;
 wire  [ 31:0]  opcode_ra_operand_w;
 
 
-riscv_csr u_csr
+riscv_csr
+u_csr
 (
     // Inputs
      .clk_i(clk_i)
@@ -152,7 +164,12 @@ riscv_csr u_csr
 );
 
 
-riscv_lsu u_lsu
+riscv_lsu
+#(
+     .MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
+    ,.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
+)
+u_lsu
 (
     // Inputs
      .clk_i(clk_i)
@@ -180,6 +197,7 @@ riscv_lsu u_lsu
     ,.mem_cacheable_o(mem_d_cacheable_o)
     ,.mem_req_tag_o(mem_d_req_tag_o)
     ,.mem_invalidate_o(mem_d_invalidate_o)
+    ,.mem_writeback_o(mem_d_writeback_o)
     ,.mem_flush_o(mem_d_flush_o)
     ,.writeback_idx_o(writeback_mem_idx_w)
     ,.writeback_squash_o(writeback_mem_squash_w)
@@ -195,7 +213,8 @@ riscv_lsu u_lsu
 );
 
 
-riscv_exec u_exec
+riscv_exec
+u_exec
 (
     // Inputs
      .clk_i(clk_i)
@@ -220,7 +239,8 @@ riscv_exec u_exec
 );
 
 
-riscv_decode u_decode
+riscv_decode
+u_decode
 (
     // Inputs
      .clk_i(clk_i)
@@ -269,7 +289,8 @@ riscv_decode u_decode
 );
 
 
-riscv_fetch u_fetch
+riscv_fetch
+u_fetch
 (
     // Inputs
      .clk_i(clk_i)

diff --git a/core/rv32i_spartan6/riscv_csr.v b/core/rv32i_spartan6/riscv_csr.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i_spartan6/riscv_decode.v b/core/rv32i_spartan6/riscv_decode.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i_spartan6/riscv_defs.v b/core/rv32i_spartan6/riscv_defs.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i_spartan6/riscv_exec.v b/core/rv32i_spartan6/riscv_exec.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //

diff --git a/core/rv32i_spartan6/riscv_fetch.v b/core/rv32i_spartan6/riscv_fetch.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.7
+//                            V0.9.8
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //