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Update RH850 code in staging #2156

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Update RH850 code in staging #2156

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1 change: 1 addition & 0 deletions include/uc_priv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#define UC_MODE_SPARC_MASK \
(UC_MODE_SPARC32 | UC_MODE_SPARC64 | UC_MODE_BIG_ENDIAN)
#define UC_MODE_M68K_MASK (UC_MODE_BIG_ENDIAN)
#define UC_MODE_RH850_MASK (UC_MODE_LITTLE_ENDIAN)
#define UC_MODE_RISCV_MASK \
(UC_MODE_RISCV32 | UC_MODE_RISCV64 | UC_MODE_LITTLE_ENDIAN)
#define UC_MODE_S390X_MASK (UC_MODE_BIG_ENDIAN)
Expand Down
51 changes: 21 additions & 30 deletions include/unicorn/rh850.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,15 +12,6 @@ extern "C" {
#pragma warning(disable : 4201)
#endif

#define UC_RH850_SYSREG_SELID0 32
#define UC_RH850_SYSREG_SELID1 64
#define UC_RH850_SYSREG_SELID2 96
#define UC_RH850_SYSREG_SELID3 128
#define UC_RH850_SYSREG_SELID4 160
#define UC_RH850_SYSREG_SELID5 192
#define UC_RH850_SYSREG_SELID6 224
#define UC_RH850_SYSREG_SELID7 256

//> RH850 global purpose registers
typedef enum uc_rh850_reg {
UC_RH850_REG_R0 = 0,
Expand Down Expand Up @@ -57,7 +48,7 @@ typedef enum uc_rh850_reg {
UC_RH850_REG_R31,

//> RH850 system registers, selection ID 0
UC_RH850_REG_EIPC = UC_RH850_SYSREG_SELID0,
UC_RH850_REG_EIPC,
UC_RH850_REG_EIPSW,
UC_RH850_REG_FEPC,
UC_RH850_REG_FEPSW,
Expand All @@ -69,43 +60,43 @@ typedef enum uc_rh850_reg {
UC_RH850_REG_FPCC,
UC_RH850_REG_FPCFG,
UC_RH850_REG_FPEC,
UC_RH850_REG_EIIC = UC_RH850_SYSREG_SELID0 + 13,
UC_RH850_REG_EIIC,
UC_RH850_REG_FEIC,
UC_RH850_REG_CTPC = UC_RH850_SYSREG_SELID0 + 16,
UC_RH850_REG_CTPC,
UC_RH850_REG_CTPSW,
UC_RH850_REG_CTBP = UC_RH850_SYSREG_SELID0 + 20,
UC_RH850_REG_EIWR = UC_RH850_SYSREG_SELID0 + 28,
UC_RH850_REG_FEWR = UC_RH850_SYSREG_SELID0 + 29,
UC_RH850_REG_BSEL = UC_RH850_SYSREG_SELID0 + 31,
UC_RH850_REG_CTBP,
UC_RH850_REG_EIWR,
UC_RH850_REG_FEWR,
UC_RH850_REG_BSEL,

//> RH850 system regusters, selection ID 1
UC_RH850_REG_MCFG0 = UC_RH850_SYSREG_SELID1,
//> RH850 system registers, selection ID 1
UC_RH850_REG_MCFG0,
UC_RH850_REG_RBASE,
UC_RH850_REG_EBASE,
UC_RH850_REG_INTBP,
UC_RH850_REG_MCTL,
UC_RH850_REG_PID,
UC_RH850_REG_SCCFG = UC_RH850_SYSREG_SELID1 + 11,
UC_RH850_REG_SCCFG,
UC_RH850_REG_SCBP,

//> RH850 system registers, selection ID 2
UC_RH850_REG_HTCFG0 = UC_RH850_SYSREG_SELID2,
UC_RH850_REG_MEA = UC_RH850_SYSREG_SELID2 + 6,
UC_RH850_REG_HTCFG0,
UC_RH850_REG_MEA,
UC_RH850_REG_ASID,
UC_RH850_REG_MEI,

UC_RH850_REG_PC = UC_RH850_SYSREG_SELID7 + 32,
UC_RH850_REG_ENDING
} uc_cpu_rh850;
UC_RH850_REG_PC,
UC_RH850_REG_ENDING,

//> RH8509 Registers aliases.
#define UC_RH850_REG_ZERO UC_RH850_REG_R0
#define UC_RH850_REG_SP UC_RH850_REG_R3
#define UC_RH850_REG_EP UC_RH850_REG_R30
#define UC_RH850_REG_LP UC_RH850_REG_R31
//> Alias registers
UC_RH850_REG_ZERO = UC_RH850_REG_R0,
UC_RH850_REG_SP = UC_RH850_REG_R3,
UC_RH850_REG_EP = UC_RH850_REG_R30,
UC_RH850_REG_LP = UC_RH850_REG_R31,
} uc_rh850_reg;

#ifdef __cplusplus
}
#endif

#endif
#endif
18 changes: 18 additions & 0 deletions qemu/include/tcg/tcg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -837,6 +837,24 @@ struct TCGContext {
TCGv cpu_eind;
TCGv cpu_sp;
TCGv cpu_skip;

// target/rh850/translate.c
TCGv rh850_cpu_sys_reg[7][32];
TCGv_i32 cpu_SF;
TCGv_i32 cpu_OVF;
TCGv_i32 cpu_CYF;
TCGv_i32 cpu_SATF;
TCGv_i32 cpu_ID;
TCGv_i32 cpu_EP;
TCGv_i32 cpu_NP;
TCGv_i32 cpu_EBV;
TCGv_i32 cpu_CU0;
TCGv_i32 cpu_CU1;
TCGv_i32 cpu_CU2;
TCGv_i32 cpu_UM;
TCGv cpu_LLbit;
TCGv cpu_LLAddress;
TCGv cpu_sys_databuf_reg;
};

static inline size_t temp_idx(TCGContext *tcg_ctx, TCGTemp *ts)
Expand Down
2 changes: 0 additions & 2 deletions qemu/rh850.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1347,7 +1347,5 @@
#define helper_stqcx_le_parallel helper_stqcx_le_parallel_rh850
#define helper_stqcx_be_parallel helper_stqcx_be_parallel_rh850
#define restore_state_to_opc restore_state_to_opc_rh850
#define helper_tlb_flush helper_tlb_flush_rh850
#define helper_uc_rh850_exit helper_uc_rh850_exit_rh850
#define gen_intermediate_code gen_intermediate_code_rh850
#endif
1 change: 0 additions & 1 deletion qemu/target/rh850/Makefile.objs
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This file was deleted.

5 changes: 3 additions & 2 deletions qemu/target/rh850/cpu-param.h
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Original file line number Diff line number Diff line change
@@ -1,11 +1,12 @@
#pragma once
#ifndef RH850_CPU_PARAM_H
#define RH850_CPU_PARAM_H

/* QEMU addressing/paging config */
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */

#define TARGET_LONG_BITS 32
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define NB_MMU_MODES 4

#endif
32 changes: 32 additions & 0 deletions qemu/target/rh850/cpu-qom.h
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Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
#ifndef QEMU_RH850_QOM_H
#define QEMU_RH850_QOM_H

#include "hw/core/cpu.h"

#define TYPE_RH850_CPU "rh850-cpu"

#define RH850_CPU(obj) ((RH850CPU *)obj)
#define RH850_CPU_CLASS(klass) ((RH850CPUClass *)klass)
#define RH850_CPU_GET_CLASS(obj) (&((RH850CPU *)obj)->cc)

typedef struct RH850CPUInfo {
const char *name;
void (*initfn)(CPUState *obj);
} RH850CPUInfo;

/**
* RH850CPUClass:
* @parent_reset: The parent class' reset handler.
*
* An RH850 CPU model.
*/
typedef struct RH850CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/

const RH850CPUInfo *info;
void (*parent_reset)(CPUState *cpu);
} RH850CPUClass;

#endif
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