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Merged
merged 14 commits into from
Oct 30, 2025
Merged

Make read_xml_arch_file more compliant with doing style #3326

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5c51b63
rename Node to node
soheilshahrouz Oct 29, 2025
307d184
rename SubTile and CurSubTile to sub_tile and cur_sub_tile
soheilshahrouz Oct 29, 2025
d6128b1
Next ---> next
soheilshahrouz Oct 29, 2025
4f10eb2
join declaration and assignment + renmae some vars
soheilshahrouz Oct 29, 2025
34bb767
use std:string for storing pin names in t_pin_to_pin_annotations
soheilshahrouz Oct 29, 2025
07a0f34
std::string for t_arch:architecture_id
soheilshahrouz Oct 29, 2025
a2418f3
std::string for input/output_string in t_interconnect
soheilshahrouz Oct 29, 2025
d744f8c
call c_str() on deafult name string
soheilshahrouz Oct 29, 2025
4ce0c34
local loop variables in arch_util.cpp
soheilshahrouz Oct 29, 2025
c4eef94
add noexcept to criteria
soheilshahrouz Oct 29, 2025
3b938f6
get rid of redundant calls to std::string constructor
soheilshahrouz Oct 29, 2025
94864ae
call c_str()
soheilshahrouz Oct 29, 2025
84dbbe2
fix forward declaration
soheilshahrouz Oct 29, 2025
8aa70b5
fixed segfault
soheilshahrouz Oct 30, 2025
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16 changes: 8 additions & 8 deletions libs/libarchfpga/src/arch_check.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -163,11 +163,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) {
//Check that any combinational delays specified match the 'combinational_sinks_ports' in the model

if (annotation.clock) {
if (!annotation.clock.empty()) {
//Sequential annotation, check that the clock on the specified port matches the model

//Annotations always put the pin in the input_pins field
VTR_ASSERT(annotation.input_pins);
// Annotations always put the pin in the input_pins field
VTR_ASSERT(!annotation.input_pins.empty());
for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
InstPort annot_port(input_pin);
for (const std::string& clock : vtr::StringToken(annotation.clock).split(" \t\n")) {
Expand Down Expand Up @@ -207,15 +207,15 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
}
}

} else if (annotation.input_pins && annotation.output_pins) {
//Combinational annotation
VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock");
} else if (!annotation.input_pins.empty() && !annotation.output_pins.empty()) {
// Combinational annotation
VTR_ASSERT_MSG(annotation.clock.empty(), "Combinational annotations should have no clock");
for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
InstPort annot_in(input_pin);
for (const std::string& output_pin : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
InstPort annot_out(output_pin);

//Find the input model port
// Find the input model port
const t_model_ports* model_port = nullptr;
for (const t_model_ports* port = model.inputs; port != nullptr; port = port->next) {
if (port->name == annot_in.port_name()) {
Expand All @@ -230,7 +230,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
annot_in.port_name().c_str(), annot_in.instance_name().c_str());
}

//Check that the output port is listed in the model's combinational sinks
// Check that the output port is listed in the model's combinational sinks
auto b = model_port->combinational_sink_ports.begin();
auto e = model_port->combinational_sink_ports.end();
auto iter = std::find(b, e, annot_out.port_name());
Expand Down
269 changes: 87 additions & 182 deletions libs/libarchfpga/src/arch_util.cpp
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2 changes: 1 addition & 1 deletion libs/libarchfpga/src/arch_util.h
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Expand Up @@ -69,7 +69,7 @@ t_logical_block_type get_empty_logical_type(const char* name = EMPTY_BLOCK_NAME)
std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type);

void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
char* new_name,
std::string_view new_name,
t_pb_type* copy);

void ProcessLutClass(t_pb_type* lut_pb_type);
Expand Down
14 changes: 7 additions & 7 deletions libs/libarchfpga/src/echo_arch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -397,12 +397,12 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) {
fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs.c_str(),
pb_type->modes[i].interconnect[j].type,
pb_type->modes[i].interconnect[j].input_string,
pb_type->modes[i].interconnect[j].output_string);
pb_type->modes[i].interconnect[j].input_string.c_str(),
pb_type->modes[i].interconnect[j].output_string.c_str());
for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) {
fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(),
annotation.input_pins,
annotation.output_pins,
annotation.input_pins.c_str(),
annotation.output_pins.c_str(),
annotation.format,
annotation.annotation_entries[0].second.c_str());
}
Expand All @@ -428,9 +428,9 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c
&& pb_type_model_name != LogicalModels::MODEL_OUTPUT) {
for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs.c_str(),
annotation.clock,
annotation.input_pins,
annotation.output_pins,
annotation.clock.c_str(),
annotation.input_pins.c_str(),
annotation.output_pins.c_str(),
annotation.format,
annotation.annotation_entries[0].second.c_str());
}
Expand Down
23 changes: 8 additions & 15 deletions libs/libarchfpga/src/physical_types.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1076,18 +1076,13 @@ struct t_pin_to_pin_annotation {
e_pin_to_pin_annotation_type type;
e_pin_to_pin_annotation_format format;

char* input_pins;
char* output_pins;
char* clock;
std::string input_pins;
std::string output_pins;
std::string clock;

int line_num; /* used to report what line number this annotation is found in architecture file */

t_pin_to_pin_annotation() noexcept {
annotation_entries = std::vector<std::pair<int, std::string>>();
input_pins = nullptr;
output_pins = nullptr;
clock = nullptr;

line_num = 0;
type = (e_pin_to_pin_annotation_type)0;
format = (e_pin_to_pin_annotation_format)0;
Expand All @@ -1113,8 +1108,8 @@ struct t_interconnect {
e_interconnect type;
char* name;

char* input_string;
char* output_string;
std::string input_string;
std::string output_string;

std::vector<t_pin_to_pin_annotation> annotations;
bool infer_annotations;
Expand All @@ -1132,8 +1127,6 @@ struct t_interconnect {
t_interconnect() {
type = (e_interconnect)0;
name = nullptr;
input_string = nullptr;
output_string = nullptr;
infer_annotations = false;
line_num = 0;
parent_mode_index = 0;
Expand Down Expand Up @@ -1971,7 +1964,7 @@ struct t_arch {
std::vector<vtr::interned_string> interned_strings;

/// Secure hash digest of the architecture file to uniquely identify this architecture
char* architecture_id;
std::string architecture_id;

// Options for tileable routing architectures
// These are used for an alternative, tilable, rr-graph generator that can produce
Expand Down Expand Up @@ -2006,12 +1999,12 @@ struct t_arch {
int sub_fs;

/// Connecting type for pass tracks in each switch block
enum e_switch_block_type sb_sub_type;
e_switch_block_type sb_sub_type;

// End of tileable architecture options

t_chan_width_dist Chans;
enum e_switch_block_type sb_type;
e_switch_block_type sb_type;
std::vector<t_switchblock_inf> switchblocks;
float R_minW_nmos;
float R_minW_pmos;
Expand Down
70 changes: 34 additions & 36 deletions libs/libarchfpga/src/read_fpga_interchange_arch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -242,28 +242,28 @@ static t_port get_generic_port(t_arch* arch,
}

/** @brief Returns true if a given port name exists in the given complex block */
static bool block_port_exists(t_pb_type* pb_type, std::string port_name) {
static bool block_port_exists(t_pb_type* pb_type, std::string_view port_name) {
for (int iport = 0; iport < pb_type->num_ports; iport++) {
const t_port port = pb_type->ports[iport];

if (std::string(port.name) == port_name)
if (port.name == port_name)
return true;
}

return false;
}

/** @brief Returns a pack pattern given it's name, input and output strings */
static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) {
/** @brief Returns a pack pattern given its name, input and output strings */
static t_pin_to_pin_annotation get_pack_pattern(std::string_view pp_name, std::string_view input, std::string_view output) {
t_pin_to_pin_annotation pp;

pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name});
pp.input_pins = vtr::strdup(input.c_str());
pp.output_pins = vtr::strdup(output.c_str());
pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name.data()});
pp.input_pins = input;
pp.output_pins = output;

pp.clock = nullptr;
pp.clock.clear();

return pp;
}
Expand Down Expand Up @@ -1216,8 +1216,8 @@ struct ArchReader {
ostr = std::string(pb_type->name) + ".in[" + std::to_string(j) + "]";
name = istr + "_to_" + ostr;

ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;
ic->name = vtr::strdup(name.c_str());
}

Expand All @@ -1231,8 +1231,8 @@ struct ArchReader {
ostr = std::string(parent->name) + "." + lut_bel.output_pin;
name = istr + "_to_" + ostr;

ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;
ic->name = vtr::strdup(name.c_str());
}
}
Expand Down Expand Up @@ -1267,14 +1267,12 @@ struct ArchReader {
mode->interconnect = new t_interconnect[mode->num_interconnect];
t_interconnect* ic = &mode->interconnect[0];

std::string istr, ostr, name;
std::string istr = std::string(pb_type->name) + ".in";
std::string ostr = std::string(pb_type->name) + ".out";
std::string name = "passthrough";

istr = std::string(pb_type->name) + ".in";
ostr = std::string(pb_type->name) + ".out";
name = "passthrough";

ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;
ic->name = vtr::strdup(name.c_str());

ic->type = COMPLETE_INTERC;
Expand Down Expand Up @@ -1329,8 +1327,8 @@ struct ArchReader {
ostr = std::string(lut->name) + ".in";
name = istr + "_to_" + ostr;

ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;
ic->name = vtr::strdup(name.c_str());

// Output
Expand All @@ -1343,8 +1341,8 @@ struct ArchReader {
ostr = std::string(pb_type->name) + ".out";
name = istr + "_to_" + ostr;

ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;
ic->name = vtr::strdup(name.c_str());
}

Expand Down Expand Up @@ -1458,15 +1456,15 @@ struct ArchReader {
o_ic->type = DIRECT_INTERC;
o_ic->parent_mode_index = 0;
o_ic->parent_mode = omode;
o_ic->input_string = vtr::strdup(opad_istr.c_str());
o_ic->output_string = vtr::strdup(opad_ostr.c_str());
o_ic->input_string = opad_istr;
o_ic->output_string = opad_ostr;

i_ic->name = vtr::strdup(i_ic_name.c_str());
i_ic->type = DIRECT_INTERC;
i_ic->parent_mode_index = 0;
i_ic->parent_mode = imode;
i_ic->input_string = vtr::strdup(ipad_istr.c_str());
i_ic->output_string = vtr::strdup(ipad_ostr.c_str());
i_ic->input_string = ipad_istr.c_str();
i_ic->output_string = ipad_ostr.c_str();

omode->interconnect[0] = *o_ic;
imode->interconnect[0] = *i_ic;
Expand Down Expand Up @@ -1611,8 +1609,8 @@ struct ArchReader {
ic->type = DIRECT_INTERC;
ic->parent_mode_index = idx;
ic->parent_mode = mode;
ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;
}

create_ports(leaf, pins, name);
Expand Down Expand Up @@ -1667,8 +1665,8 @@ struct ArchReader {
ic->type = ic_type;
ic->parent_mode_index = idx;
ic->parent_mode = mode;
ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;
}

/** @brief Processes all the ports of a given complex block.
Expand Down Expand Up @@ -1787,8 +1785,8 @@ struct ArchReader {

VTR_ASSERT(names.insert(ic_name).second);
ic->name = vtr::strdup(ic_name.c_str());
ic->input_string = vtr::strdup(input.c_str());
ic->output_string = vtr::strdup(outputs_str.c_str());
ic->input_string = input;
ic->output_string = outputs_str;
}

// Checks and, in case, adds all the necessary pack patterns to the marked interconnects
Expand Down Expand Up @@ -2144,8 +2142,8 @@ struct ArchReader {
ic->type = DIRECT_INTERC;
ic->parent_mode_index = 0;
ic->parent_mode = mode;
ic->input_string = vtr::strdup(istr.c_str());
ic->output_string = vtr::strdup(ostr.c_str());
ic->input_string = istr;
ic->output_string = ostr;

count++;
}
Expand Down Expand Up @@ -2529,7 +2527,7 @@ void FPGAInterchangeReadArch(const char* FPGAInterchangeDeviceFile,

auto device_reader = message_reader.getRoot<DeviceResources::Device>();

arch->architecture_id = vtr::strdup(vtr::secure_digest_file(FPGAInterchangeDeviceFile).c_str());
arch->architecture_id = vtr::secure_digest_file(FPGAInterchangeDeviceFile);

ArchReader reader(arch, device_reader, FPGAInterchangeDeviceFile, PhysicalTileTypes, LogicalBlockTypes);
reader.read_arch();
Expand Down
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