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Setting IPIN Tdel #3346

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57837db
[libs][rr_graph] set T_linear for IPIN based on the most frequent swi…
amin1377 Nov 17, 2025
129fd88
[libs][rr_graph] print a warning if IPIN switch block doesn't match t…
amin1377 Nov 17, 2025
4dd6a63
[lib][rr_graph] add const identifier for const params passed to calcu…
amin1377 Nov 17, 2025
a94742a
[lib][rr_graph][rr_indexed] use avg ipin for t_linear when building R…
amin1377 Nov 19, 2025
a0e4de9
fix a typo
amin1377 Nov 19, 2025
6228a71
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Nov 20, 2025
2298aec
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Nov 20, 2025
9d025f2
[ci] update vtr_reg_strong_odin/strong_global_nonuniform/config/golde…
amin1377 Nov 20, 2025
439c236
[ci] update goldne for stron_ap strong_bidir and strong_cock_aliases
amin1377 Nov 20, 2025
6094a6f
[ci] update strong_custom_grid strong_sdc strong_soft_multipliers
amin1377 Nov 20, 2025
918a10f
[ci] update strong_bidir golden resutls
amin1377 Nov 21, 2025
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53 changes: 44 additions & 9 deletions libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@

#include <algorithm>
#include <cmath> /* Needed only for sqrt call (remove if sqrt removed) */
#include <cstddef>
#include <fstream>
#include <iomanip>
#include <numeric>
Expand All @@ -28,7 +29,9 @@ static void load_rr_indexed_data_base_costs(const RRGraphView& rr_graph,

static float get_delay_normalization_fac(const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data, const bool echo_enabled, const char* echo_file_name);

static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data);
static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
const RRSwitchId wire_to_ipin_switch,
vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data);

/**
* @brief Computes average R, Tdel, and Cinternal of fan-in switches for a given node.
Expand All @@ -49,7 +52,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph,
int& num_switches,
int& num_shorts,
short& buffered,
vtr::vector<RRNodeId, std::vector<RREdgeId>>& fan_in_list);
const vtr::vector<RRNodeId, std::vector<RREdgeId>>& fan_in_list);

static void fixup_rr_indexed_data_T_values(vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data, size_t num_segment);

Expand Down Expand Up @@ -84,7 +87,7 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
const std::vector<t_segment_inf>& segment_inf_y,
const std::vector<t_segment_inf>& segment_inf_z,
vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data,
RRSwitchId wire_to_ipin_switch,
const RRSwitchId wire_to_ipin_switch,
e_base_cost_type base_cost_type,
const bool echo_enabled,
const char* echo_file_name) {
Expand All @@ -108,9 +111,6 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
rr_indexed_data[RRIndexedDataId(i)].C_load = 0.;
}

//TODO: SM: IPIN t_linear assumes wire_to_ipin_switch which corresponds to within die switch connection
rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = rr_graph.rr_switch_inf(wire_to_ipin_switch).Tdel;

std::vector<int> ortho_costs = find_ortho_cost_index(rr_graph, segment_inf_x, segment_inf_y, e_parallel_axis::X_AXIS);

/* AA: The code below should replace find_ortho_cost_index call once we deprecate the CLASSIC lookahead as it is the only lookahead
Expand Down Expand Up @@ -158,7 +158,9 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
rr_indexed_data[index].seg_index = seg_ptr->seg_index;
}

load_rr_indexed_data_T_values(rr_graph, rr_indexed_data);
load_rr_indexed_data_T_values(rr_graph,
wire_to_ipin_switch,
rr_indexed_data);

fixup_rr_indexed_data_T_values(rr_indexed_data, total_num_segment);

Expand Down Expand Up @@ -513,6 +515,7 @@ static float get_delay_normalization_fac(const vtr::vector<RRIndexedDataId, t_rr
* - Placement Delay Matrix computation
*/
static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
const RRSwitchId wire_to_ipin_switch,
vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data) {
vtr::vector<RRNodeId, std::vector<RREdgeId>> fan_in_list = get_fan_in_list(rr_graph);

Expand All @@ -531,12 +534,24 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
vtr::vector<RRIndexedDataId, std::vector<float>> switch_Cinternal_total(rr_indexed_data.size());
vtr::vector<RRIndexedDataId, short> switches_buffered(rr_indexed_data.size(), LIBRRGRAPH_UNDEFINED_VAL);

size_t ipin_switch_count = 0;
float ipin_switch_T_total = 0.;

// Walk through the RR graph and collect all R and C values of all the nodes,
// as well as their fan-in switches R, T_del, and Cinternal values.
// The median of R and C values for each cost index is assigned to the indexed data.
for (const RRNodeId rr_id : rr_graph.nodes()) {
e_rr_type rr_type = rr_graph.node_type(rr_id);

if (rr_type == e_rr_type::IPIN) {
for (const RREdgeId edge : fan_in_list[rr_id]) {
RRSwitchId rr_switch_id = RRSwitchId(rr_graph.edge_switch(edge));
float switch_T_del = rr_graph.rr_switch_inf(rr_switch_id).Tdel;
ipin_switch_T_total += switch_T_del;
ipin_switch_count++;
}
}

if (!is_chanxy(rr_type) && !is_chanz(rr_type)) {
continue;
}
Expand All @@ -550,7 +565,15 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
int num_switches = 0;
int num_shorts = 0;
short buffered = LIBRRGRAPH_UNDEFINED_VAL;
calculate_average_switch(rr_graph, rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list);
calculate_average_switch(rr_graph,
rr_id,
avg_switch_R,
avg_switch_T,
avg_switch_Cinternal,
num_switches,
num_shorts,
buffered,
fan_in_list);

if (num_switches == 0) {
if (num_shorts == 0) {
Expand Down Expand Up @@ -590,6 +613,18 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
}
}

// Set the T_linear value for the IPIN cost index
{
if (ipin_switch_count == 0) {
VTR_LOG_WARN("No IPIN switches found. Setting T_linear to 0\n");
float default_ipin_switch_T_del = rr_graph.rr_switch_inf(RRSwitchId(wire_to_ipin_switch)).Tdel;
rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = default_ipin_switch_T_del;
} else {
float average_ipin_switch_T_del = ipin_switch_T_total / ipin_switch_count;
rr_indexed_data[RRIndexedDataId(IPIN_COST_INDEX)].T_linear = average_ipin_switch_T_del;
}
}

unsigned num_occurences_of_no_instances_with_cost_index = 0;
for (size_t cost_index = CHANX_COST_INDEX_START; cost_index < rr_indexed_data.size(); cost_index++) {
if (num_nodes_of_index[RRIndexedDataId(cost_index)] == 0) { // Segments don't exist.
Expand Down Expand Up @@ -650,7 +685,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph,
int& num_switches,
int& num_shorts,
short& buffered,
vtr::vector<RRNodeId, std::vector<RREdgeId>>& fan_in_list) {
const vtr::vector<RRNodeId, std::vector<RREdgeId>>& fan_in_list) {

avg_switch_R = 0;
avg_switch_T = 0;
Expand Down
2 changes: 1 addition & 1 deletion libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
const std::vector<t_segment_inf>& segment_inf_y,
const std::vector<t_segment_inf>& segment_inf_z,
vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data,
RRSwitchId wire_to_ipin_switch,
const RRSwitchId wire_to_ipin_switch,
e_base_cost_type base_cost_type,
const bool echo_enabled,
const char* echo_file_name);
Expand Down
2 changes: 1 addition & 1 deletion .../regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.64 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 135 9 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 77064 9 19 896 28 0 660 163 16 16 256 -1 mcnc_medium -1 -1 7727.83 7087 9508 603 6937 1968 75.3 MiB 2.09 0.00 6.3343 5.39115 -88.0884 -5.39115 nan 0.00 0.00133719 0.00116801 0.0488072 0.0445052 75.3 MiB 2.09 75.3 MiB 1.41 11108 16.8558 2920 4.43096 4709 24240 778883 128039 1.05632e+07 7.27569e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72644 nan -92.7439 -5.72644 0 0 0.13 -1 -1 75.3 MiB 0.25 0.223627 0.205422 31.2 MiB -1 0.04
k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.64 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 130 9 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 77064 9 19 896 28 0 660 163 16 16 256 -1 mcnc_medium -1 -1 7727.83 7087 9508 603 6937 1968 75.3 MiB 2.09 0.00 6.3343 5.39115 -88.0884 -5.39115 nan 0.00 0.00133719 0.00116801 0.0488072 0.0445052 75.3 MiB 2.09 75.3 MiB 1.41 11108 16.8558 2920 4.43096 4709 24240 778883 128039 1.05632e+07 7.27569e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72644 nan -92.7439 -5.72644 0 0 0.13 -1 -1 75.3 MiB 0.25 0.223627 0.205422 31.2 MiB -1 0.04
k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.54 vpr 76.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 173 256 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 78236 256 245 954 501 0 760 674 22 22 484 -1 mcnc_large -1 -1 9292.95 7827 56800 1790 18880 36130 76.4 MiB 1.08 0.01 5.23911 4.45825 -854.38 -4.45825 nan 0.00 0.00195959 0.0018456 0.0499366 0.0472422 76.4 MiB 1.08 76.4 MiB 0.81 11106 14.6132 3086 4.06053 2658 7145 291226 67335 2.15576e+07 9.32366e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.93512 nan -901.874 -4.93512 0 0 0.15 -1 -1 76.4 MiB 0.16 0.143878 0.136836 33.7 MiB -1 0.05
k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.76 vpr 76.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 147 41 -1 -1 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 78320 41 35 1006 76 0 714 223 16 16 256 -1 mcnc_medium -1 -1 9169.27 7694 8335 415 5173 2747 76.5 MiB 2.20 0.01 6.36629 5.23793 -151.219 -5.23793 nan 0.00 0.0015282 0.00132775 0.0366109 0.0336215 76.5 MiB 2.20 76.5 MiB 1.46 12142 17.0056 3244 4.54342 4212 22271 689032 117413 1.05632e+07 7.92242e+06 1.26944e+06 4958.75 16 28900 206586 -1 5.65269 nan -156.023 -5.65269 0 0 0.13 -1 -1 76.5 MiB 0.24 0.22311 0.205529 31.8 MiB -1 0.04
2 changes: 1 addition & 1 deletion vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt
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Expand Up @@ -2,4 +2,4 @@
k4_n4_v7_bidir.xml styr.blif common 1.37 vpr 62.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64104 10 10 253 263 1 171 92 11 11 121 clb auto 23.5 MiB 0.04 1829.24 1329 4646 728 3820 98 62.6 MiB 0.05 0.00 8.75156 5.65828 -74.3763 -5.65828 5.65828 0.08 0.000539066 0.000438929 0.0158895 0.0133045 -1 -1 -1 -1 14 1972 27 2.43e+06 2.16e+06 -1 -1 0.65 0.146019 0.12287 3402 27531 -1 1970 16 1168 4226 219209 27455 7.33108 7.33108 -92.5065 -7.33108 0 0 -1 -1 0.01 0.07 0.02 -1 -1 0.01 0.0241699 0.0213263
k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 63.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64704 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1305 3404 389 2964 51 63.2 MiB 0.04 0.00 5.19817 4.46893 -53.8773 -4.46893 4.46893 0.09 0.000510361 0.000414222 0.0114433 0.00959255 -1 -1 -1 -1 18 2312 35 2.43e+06 2.16e+06 -1 -1 1.02 0.19335 0.161505 3282 34431 -1 2326 21 1300 4425 297597 37882 9.34193 9.34193 -107.688 -9.34193 0 0 -1 -1 0.02 0.09 0.03 -1 -1 0.02 0.0293867 0.0256624
k4_n4_v7_l1_bidir.xml styr.blif common 1.82 vpr 62.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64084 10 10 253 263 1 171 92 11 11 121 clb auto 23.7 MiB 0.04 1829.24 1283 8993 1996 6843 154 62.6 MiB 0.10 0.00 11.3865 6.82489 -85.7025 -6.82489 6.82489 0.10 0.000535759 0.000437145 0.0267342 0.0222548 -1 -1 -1 -1 10 1437 37 2.43e+06 2.16e+06 -1 -1 0.95 0.1205 0.101293 4482 22551 -1 1348 24 1290 4977 336418 74151 8.81482 8.81482 -100.507 -8.81482 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0332838 0.0290833
k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -323.027 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146
k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 vpr 63.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success b2bdea1 Release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-06-18T23:25:54 pkrvmxyh4eaekms /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64736 10 10 253 263 1 171 92 11 11 121 clb auto 23.6 MiB 0.04 1829.24 1294 4025 499 3414 112 63.2 MiB 0.05 0.00 4.50889 3.4607 -44.4554 -3.4607 3.4607 0.09 0.00054143 0.000441935 0.0136548 0.0114763 -1 -1 -1 -1 16 2079 28 2.43e+06 2.16e+06 -1 -1 1.10 0.148452 0.124941 3522 30407 -1 2152 25 1482 5545 978183 174036 26.5946 26.5946 -260 -26.5946 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0329671 0.0287146
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