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Adding a New Sample(s)

Description

This project demonstrates how to use SYCL HLS to create a 2D Convolution IP that can be used in your Intel® Quartus® Prime projects.

Purpose

This project demonstrates how to use SYCL HLS to create a 2D Convolution IP that can be used in your Intel® Quartus® Prime projects. Convolution is a cornerstone problem in video processing designs. It commonly appears in both hardware and software systems, but in general, software implementations do not efficiently synthesize into RTL. This reference design includes:

  • A re-usable C++ library that generates an efficient line buffer hardware module. This hardware module is the foundation of convolution algorithms, and other similar algorithms.

  • An example of how to chain together multiple video processing modules using sycl::pipes, which behave like streaming interfaces in hardware designs.

  • A video-processing testbench that you can use to test your own designs. This testbench consumes image data from RAM and parcels it into streaming transactions. This makes it easy to 'stream' a test image into your video design.

Checklist

Administrative

  • Review sample design with the appropriate Domain Expert: Paul White
  • If you have any new dependencies/binaries, inform the oneAPI Code Samples Project Manager

Code Development

Security and Legal

  • OSPDT Approval (see Project Manager for assistance)
  • Compile using the following compiler flags and fix any warnings, the falgs are: "/Wall -Wformat-security -Werror=format-security"
  • Bandit Scans (Python only)
  • Virus scan

Review

  • Review DPC++ code with Paul Peterseon. (GitHub User: pmpeter1)
  • Review readme with Tom Lenth(@tomlenth) and/or Project Manager
  • Tested using Dev Cloud when applicable

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