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XJTUIAIR-CAG

Cognitive Architecture Group, Institute of AI & Robitics, Xi'an Jiaotong Univiersity

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  1. XJTU-Tripler XJTU-Tripler Public

    XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

    VHDL 176 45

  2. Matterhorn Matterhorn Public

    A novel general neuromorphic computing framework based on PyTorch.

    Python 13 2

  3. Vscale_plus Vscale_plus Public

    A 3-stage in-order single-scalar RISC-V processor

    Verilog 11 3

  4. SiYuan SiYuan Public

    A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS

    SystemVerilog 7 1

  5. gem5_dda gem5_dda Public

    A gem5 experimental repo in order to explore Data-dependent Access (DDA).

    C++ 6 4

  6. c910-fpga c910-fpga Public

    An FPGA project of a simple SOC witn Xuantie c906

    TeX 5 3

Repositories

Showing 9 of 9 repositories
  • SiYuan Public

    A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS

    xjtuiair-cag/SiYuan’s past year of commit activity
    SystemVerilog 7 1 1 0 Updated Apr 2, 2025
  • SiYuan-sdk Public Forked from openhwgroup/cva6-sdk

    SiYuan SDK containing RISC-V tools and Buildroot

    xjtuiair-cag/SiYuan-sdk’s past year of commit activity
    C 0 73 0 0 Updated Apr 2, 2025
  • Matterhorn Public

    A novel general neuromorphic computing framework based on PyTorch.

    xjtuiair-cag/Matterhorn’s past year of commit activity
    Python 13 MIT-0 2 0 0 Updated Jan 21, 2025
  • gem5_dda Public

    A gem5 experimental repo in order to explore Data-dependent Access (DDA).

    xjtuiair-cag/gem5_dda’s past year of commit activity
    C++ 6 BSD-3-Clause 4 0 0 Updated Jun 5, 2024
  • c910-fpga Public

    An FPGA project of a simple SOC witn Xuantie c906

    xjtuiair-cag/c910-fpga’s past year of commit activity
    TeX 5 3 1 0 Updated May 17, 2024
  • xjtuiair-cag/xjtucag-benchmarks’s past year of commit activity
    Fortran 1 0 0 0 Updated Apr 24, 2024
  • XJTU-Tripler Public

    XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

    xjtuiair-cag/XJTU-Tripler’s past year of commit activity
    VHDL 176 45 0 0 Updated Jan 10, 2024
  • dmp Public

    Dmp: differential matching prefetcher

    xjtuiair-cag/dmp’s past year of commit activity
    1 MIT 0 0 0 Updated Dec 22, 2023
  • Vscale_plus Public

    A 3-stage in-order single-scalar RISC-V processor

    xjtuiair-cag/Vscale_plus’s past year of commit activity
    Verilog 11 3 0 0 Updated Oct 24, 2019

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