RMII 8b tx

Jenkinsfile

@@ -248,4 +248,4 @@ pipeline {
       }
     }
   } // stages
-} // pipeline
+} // pipeline

doc/rst/lib_ethernet.rst

@@ -1041,7 +1041,7 @@ Real-time Ethernet MAC supporting typedefs
 
 .. doxygenenum:: ethernet_enable_shaper_t
 .. doxygenstruct:: rmii_port_timing_t
-.. doxygenenum:: rmii_data_4b_pin_assignment_t
+.. doxygenenum:: rmii_data_pin_assignment_t
 
 
 |newpage|

examples/app_ethernet_diagnostics/src/main.xc

@@ -27,7 +27,6 @@ port p_phy_clk = RMII_PHY_CLK_50M;
 clock phy_rxclk = on tile[0]: XS1_CLKBLK_1;
 clock phy_txclk = on tile[0]: XS1_CLKBLK_2;
 
-
 // An enum to manage the array of connections from the ethernet component to its clients.
 enum eth_clients {
   ETH_TO_TRAFFIC,

lib_ethernet/api/ethernet.h

@@ -199,8 +199,6 @@ typedef interface ethernet_cfg_if {
    *
    *  \param ifnum   The index of the MAC interface to set the slope (always 0)
    *  \param slope   The slope value in bits per 100 MHz ref timer tick in MII_CREDIT_FRACTIONAL_BITS Q format.
-   *
-   *
    */
   void set_egress_qav_idle_slope(size_t ifnum, unsigned slope);
 
@@ -209,8 +207,6 @@ typedef interface ethernet_cfg_if {
    *
    *  \param ifnum            The index of the MAC interface to set the slope (always 0)
    *  \param bits_per_second  The maximum number of bits per second to be set
-   *
-   *
    */
   void set_egress_qav_idle_slope_bps(size_t ifnum, unsigned bits_per_second);
 
@@ -663,11 +659,16 @@ void mii_ethernet_mac(SERVER_INTERFACE(ethernet_cfg_if, i_cfg[n_cfg]), static_co
 
 /** ENUM to determine which two bits of a four bit port are to be used as data lines
  *  in the case that a four bit port is specified for RMII. The other two pins of the four bit
- *  port cannot be used. For Rx the unused input bits are ignored. For Tx, the unused pins are always driven low. */
-typedef enum rmii_data_4b_pin_assignment_t{
+ *  port cannot be used. For Rx the input values are ignored. For Tx, the unused pins are always driven low. */
+typedef enum rmii_data_pin_assignment_t{
     USE_LOWER_2B = 0,                      /**< Use bit 0 and bit 1 of the four bit port for data bits 0 and 1*/
     USE_UPPER_2B = 1                       /**< Use bit 2 and bit 3 of the four bit port for data bits 0 and 1*/
-} rmii_data_4b_pin_assignment_t;
+} rmii_data_pin_assignment_t;
+
+
+/** Macro to populate which bits of the 8b port are used in the initialiser. Unused bits are driven low. */
+#define RMII_8B_PINS_INITIALISER(pos_0, pos_1) ((unsigned)pos_0 | ((unsigned)pos_1) << 16)
+
 
 /** Struct containing the clock delay settings for the Rx and Tx pins. This is needed to adjust
  *  port timings to ensure that the data is captured with sufficient setup and hold margin.
@@ -708,13 +709,16 @@ typedef struct rmii_port_timing_t{
  *  \param rx_pin_map          Which pins to use in 4 bit case. USE_LOWER_2B or USE_HIGHER_2B. Ignored if 1 bit ports used.
  *  \param p_rxdv              RMII RX data valid port
  *  \param p_txen              RMII TX enable port
- *  \param p_txd_0             Port for data bit 0 (1 bit option) or entire port (4 bit option)
+ *  \param p_txd_0             Port for data bit 0 (1 bit option) or entire port (4 or 8 bit option)
  *  \param p_txd_1             Port for data bit 1 (1 bit option). Pass null if unused.
  *  \param tx_pin_map          Which pins to use in 4 bit case. USE_LOWER_2B or USE_HIGHER_2B. Ignored if 1 bit ports used.
+ *                             In the case of 8b port usage, the lower 16b word holds the position of the data bit 0 and
+ *                             the upper 16b word holds the position of data bit 1. Values 0..7 are valid. You can use the
+ *                             RMII_8B_PINS_INITIALISER(pos_0, pos_1) macro to initialise this value.
  *  \param rxclk               Clock used for RMII receive timing
  *  \param txclk               Clock used for RMII transmit timing
  *  \param port_timing         Struct used for initialising the clock blocks to ensure setup and hold times are met
- *
+ * 
  *  \param rx_bufsize_words    The number of words to used for a receive buffer.
  *                             This should be at least 500 long words.
  *  \param tx_bufsize_words    The number of words to used for a transmit buffer.
@@ -730,10 +734,10 @@ void rmii_ethernet_rt_mac(SERVER_INTERFACE(ethernet_cfg_if, i_cfg[n_cfg]), stati
                           nullable_streaming_chanend_t c_rx_hp,
                           nullable_streaming_chanend_t c_tx_hp,
                           in_port_t p_clk,
-                          port p_rxd_0, NULLABLE_RESOURCE(port, p_rxd_1), rmii_data_4b_pin_assignment_t rx_pin_map,
+                          port p_rxd_0, NULLABLE_RESOURCE(port, p_rxd_1), rmii_data_pin_assignment_t rx_pin_map,
                           in_port_t p_rxdv,
                           out_port_t p_txen,
-                          port p_txd_0, NULLABLE_RESOURCE(port, p_txd_1), rmii_data_4b_pin_assignment_t tx_pin_map,
+                          port p_txd_0, NULLABLE_RESOURCE(port, p_txd_1), rmii_data_pin_assignment_t tx_pin_map,
                           clock rxclk,
                           clock txclk,
                           rmii_port_timing_t port_timing,

lib_ethernet/src/mii_ethernet_rt_mac.xc

@@ -437,7 +437,7 @@ unsafe void mii_ethernet_server(mii_mempool_t rx_mem,
       if (speed < 0 || speed >= NUM_ETHERNET_SPEEDS) {
         fail("Invalid Ethernet speed, must be a valid ethernet_speed_t enum value");
       }
-      p_port_state->ingress_ts_latency[speed] = value / 10; // div by 10 to get to timer ticks from nanonseconds
+      p_port_state->ingress_ts_latency[speed] = value / 10; // div by 10 to get to timer ticks from nanonseconds 
       break;
     }
 

lib_ethernet/src/rmii_ethernet_rt_mac.xc

@@ -45,10 +45,10 @@ void rmii_ethernet_rt_mac(SERVER_INTERFACE(ethernet_cfg_if, i_cfg[n_cfg]), stati
                           nullable_streaming_chanend_t c_rx_hp,
                           nullable_streaming_chanend_t c_tx_hp,
                           in_port_t p_clk,
-                          port p_rxd_0, NULLABLE_RESOURCE(port, p_rxd_1), rmii_data_4b_pin_assignment_t rx_pin_map,
+                          port p_rxd_0, NULLABLE_RESOURCE(port, p_rxd_1), rmii_data_pin_assignment_t rx_pin_map,
                           in_port_t p_rxdv,
                           out_port_t p_txen,
-                          port p_txd_0, NULLABLE_RESOURCE(port, p_txd_1), rmii_data_4b_pin_assignment_t tx_pin_map,
+                          port p_txd_0, NULLABLE_RESOURCE(port, p_txd_1), rmii_data_pin_assignment_t tx_pin_map,
                           clock rxclk,
                           clock txclk,
                           rmii_port_timing_t port_timing,
@@ -130,12 +130,14 @@ void rmii_ethernet_rt_mac(SERVER_INTERFACE(ethernet_cfg_if, i_cfg[n_cfg]), stati
     out buffered port:32 * unsafe tx_data_0 = NULL;
     out buffered port:32 * unsafe tx_data_1 = NULL;
 
+    // Extract port info
     unsigned tx_port_width = ((unsigned)(p_txd_0) >> 16) & 0xff;
 
     switch(tx_port_width){
+      case 8:
       case 4:
         tx_data_0 = enable_buffered_out_port((unsigned*)(&p_txd_0), 32);
-        rmii_master_init_tx_4b(p_clk, tx_data_0, p_txen, txclk, port_timing);
+        rmii_master_init_tx_4b_8b(p_clk, tx_data_0, p_txen, txclk, port_timing);
         break;
       case 1:
         tx_data_0 = enable_buffered_out_port((unsigned*)&p_txd_0, 32);

lib_ethernet/src/rmii_master.h

@@ -21,11 +21,11 @@ unsafe void rmii_master_init_rx_1b( in port p_clk,
                                     clock rxclk,
                                     rmii_port_timing_t port_timing);
 
-unsafe void rmii_master_init_tx_4b( in port p_clk,
-                                    out buffered port:32 * unsafe tx_data,
-                                    out port p_txen,
-                                    clock txclk,
-                                    rmii_port_timing_t port_timing);
+unsafe void rmii_master_init_tx_4b_8b( in port p_clk,
+                                       out buffered port:32 * unsafe tx_data,
+                                       out port p_txen,
+                                       clock txclk,
+                                       rmii_port_timing_t port_timing);
 
 unsafe void rmii_master_init_tx_1b( in port p_clk,
                                     out buffered port:32 * unsafe tx_data_0,
@@ -39,7 +39,7 @@ unsafe void rmii_master_rx_pins_4b(mii_mempool_t rx_mem,
                                 unsigned * unsafe rdptr,
                                 in port p_mii_rxdv,
                                 in buffered port:32 * unsafe p_mii_rxd,
-                                rmii_data_4b_pin_assignment_t rx_port_4b_pins,
+                                rmii_data_pin_assignment_t rx_port_4b_pins,
                                 volatile int * unsafe running_flag_ptr,
                                 chanend c_rx_pins_exit);
 
@@ -60,7 +60,7 @@ unsafe void rmii_master_tx_pins(mii_mempool_t tx_mem_lp,
                                 unsigned tx_port_width,
                                 out buffered port:32 * unsafe p_mii_txd_0,
                                 out buffered port:32 * unsafe  p_mii_txd_1,
-                                rmii_data_4b_pin_assignment_t tx_port_4b_pins,
+                                rmii_data_pin_assignment_t tx_port_pins,
                                 clock txclk,
                                 volatile ethernet_port_state_t * unsafe p_port_state,
                                 volatile int * unsafe running_flag_ptr);