safe timeout, PWM align and pre-release #17
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Conflicts: lib_sw_dac/src/standard_fidelity/sigma_delta_1_5.S
uvvpavel
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Looks good. Putting the review as a comment for now, as I've asked some questions.
Conflicts: CHANGELOG.rst README.rst lib_sw_dac/src/standard_fidelity/sdac_sf.h
test_idle now expects properly offsetted PWM vals
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assert on timedout in SD test Clean timeout at startup in SD test
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Uses a select to input the upsampled PCM into SD/PWM and times out, producing a 50:50 PWM output if no sample is received.
PWM alignment after timeout included. See #21