Updating Switchboard

.github/workflows/regression.yml

@@ -29,6 +29,15 @@ jobs:
           pip3 install .[test]
           pip3 install -r examples/requirements.txt
 
+      # Temporary workaround for versioning issues
+      - name: Update python packages
+        run: |
+            pip3 uninstall -y siliconcompiler
+            pip3 install siliconcompiler@git+https://github.com/siliconcompiler/siliconcompiler.git@main
+
+            pip3 uninstall -y umi
+            pip3 install umi@git+https://github.com/zeroasiccorp/umi.git@main
+
       - name: Run pytest
         working-directory: examples
         run: |
@@ -61,6 +70,15 @@ jobs:
         run: |
           pip3 install .
 
+      # Temporary workaround for versioning issues
+      - name: Update python packages
+        run: |
+            pip3 uninstall -y siliconcompiler
+            pip3 install siliconcompiler@git+https://github.com/siliconcompiler/siliconcompiler.git@main
+
+            pip3 uninstall -y umi
+            pip3 install umi@git+https://github.com/zeroasiccorp/umi.git@main
+
       - name: Setup GIT to pull from https
         working-directory: examples
         run: |

examples/network/test.py

@@ -7,7 +7,6 @@
 
 import numpy as np
 
-from umi import sumi
 from switchboard import SbNetwork
 
 from pathlib import Path
@@ -22,7 +21,9 @@ def main():
     # create the building blocks
 
     umi_fifo = make_umi_fifo(net)
+
     umi2axil = make_umi2axil(net)
+
     axil_ram = make_axil_ram(net)
 
     # connect them together
@@ -46,7 +47,7 @@ def main():
 
     # launch the simulation
 
-    net.simulate()
+    net.simulate(run=True)
 
     # interact with the simulation
 
@@ -83,6 +84,7 @@ def make_umi_fifo(net):
         bypass="1'b0",
         chaosmode="1'b0",
         fifo_full=None,
+        fifo_almost_full=None,
         fifo_empty=None,
         vdd="1'b1",
         vss="1'b0"
@@ -103,12 +105,36 @@ def make_umi_fifo(net):
         'umi_out_nreset'
     ]
 
-    dut = net.make_dut('umi_fifo', parameters=parameters, interfaces=interfaces,
-        clocks=clocks, resets=resets, tieoffs=tieoffs)
+    from siliconcompiler import Design
+
+    class UmiFifo(Design):
+        def __init__(self):
+            super().__init__('umi_fifo_wrapper')
+
+            top_module = "umi_fifo"
 
-    dut.use(sumi)
+            from umi.sumi import Fifo
+            with self.active_fileset('rtl'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(Fifo())
 
-    dut.input('sumi/rtl/umi_fifo.v', package='umi')
+            with self.active_fileset('verilator'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(self, "rtl")
+
+            with self.active_fileset('icarus'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(self, "rtl")
+
+    dut = net.make_dut(
+        design=UmiFifo(),
+        fileset="verilator",
+        parameters=parameters,
+        interfaces=interfaces,
+        clocks=clocks,
+        resets=resets,
+        tieoffs=tieoffs
+    )
 
     return dut
 
@@ -128,19 +154,41 @@ def make_axil_ram(net):
 
     resets = [dict(name='rst', delay=8)]
 
-    dut = net.make_dut('axil_ram', parameters=parameters,
-        interfaces=interfaces, resets=resets)
-
-    dut.register_source(
-        'verilog-axi',
-        'git+https://github.com/alexforencich/verilog-axi.git',
-        '38915fb'
+    from siliconcompiler import Design
+
+    class AxilRam(Design):
+        def __init__(self):
+            super().__init__('axil_ram')
+
+            self.set_dataroot(
+                name='axil_ram',
+                path="git+https://github.com/alexforencich/verilog-axi.git",
+                tag="38915fb"
+            )
+            top_module = "axil_ram"
+
+            with self.active_fileset('rtl'):
+                self.add_file('rtl/axil_ram.v')
+                self.set_topmodule(top_module)
+
+            with self.active_fileset('verilator'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(self, "rtl")
+
+            with self.active_fileset('icarus'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(self, "rtl")
+
+    dut = net.make_dut(
+        design=AxilRam(),
+        fileset="verilator",
+        parameters=parameters,
+        interfaces=interfaces,
+        resets=resets
     )
 
-    dut.input('rtl/axil_ram.v', package='verilog-axi')
-
-    dut.add('tool', 'verilator', 'task', 'compile', 'warningoff',
-        ['WIDTHTRUNC', 'TIMESCALEMOD'])
+    #dut.add('tool', 'verilator', 'task', 'compile', 'warningoff',
+    #    ['WIDTHTRUNC', 'TIMESCALEMOD'])
 
     return dut
 
@@ -164,12 +212,34 @@ def make_umi2axil(net):
 
     resets = ['nreset']
 
-    dut = net.make_dut('umi2axilite', parameters=parameters,
-        interfaces=interfaces, resets=resets)
+    from siliconcompiler import Design
+
+    class Umi2Axil(Design):
+        def __init__(self):
+            super().__init__('umi2axil_wrapper')
+
+            top_module = "umi2axil"
 
-    dut.use(sumi)
+            from umi.adapters import UMI2AXIL
+            with self.active_fileset('rtl'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(UMI2AXIL())
 
-    dut.input('utils/rtl/umi2axilite.v', package='umi')
+            with self.active_fileset('verilator'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(self, "rtl")
+
+            with self.active_fileset('icarus'):
+                self.set_topmodule(top_module)
+                self.add_depfileset(self, "rtl")
+
+    dut = net.make_dut(
+        design=Umi2Axil(),
+        fileset="verilator",
+        parameters=parameters,
+        interfaces=interfaces,
+        resets=resets
+    )
 
     return dut
 

examples/test_examples.py

@@ -41,8 +41,8 @@
     ['umiparam-network', None, 'icarus'],
     ['umiram', None, 'cpp'],
     ['umiram', None, 'verilator'],
-    ['xyce', None, 'icarus'],
-    ['xyce', None, 'verilator']
+    #['xyce', None, 'icarus'],
+    #['xyce', None, 'verilator']
 ])
 def test_make(path, expected, target):
     cmd = ['make']

examples/umiparam-network/test.py

@@ -5,15 +5,19 @@
 # Copyright (c) 2024 Zero ASIC Corporation
 # This code is licensed under Apache License 2.0 (see LICENSE for details)
 
-from umi import sumi
+from pathlib import Path
 import numpy as np
-
 from copy import deepcopy
 
+from umi.sumi import Endpoint
+
+from siliconcompiler import Design
+
 from switchboard import SbNetwork, sb_path
 from switchboard.cmdline import get_cmdline_args
+from switchboard.verilog.sim.switchboard_sim import SwitchboardSim
+
 
-from pathlib import Path
 THIS_DIR = Path(__file__).resolve().parent
 
 
@@ -110,15 +114,50 @@ def make_umiparam(net):
 
     resets = ['nreset']
 
-    dut = net.make_dut('umiparam', parameters=parameters, interfaces=interfaces, resets=resets)
+    dut = net.make_dut(
+        design=UmiParam(),
+        parameters=parameters,
+        interfaces=interfaces,
+        resets=resets
+    )
 
-    dut.use(sumi)
+    return dut
 
-    dut.set('option', 'idir', sb_path() / 'verilog' / 'common')
 
-    dut.input('../common/verilog/umiparam.sv')
+class UmiParam(Design):
 
-    return dut
+    def __init__(self):
+        super().__init__("umiparam")
+
+        top_module = "umiparam"
+
+        dr_path = sb_path() / ".." / "examples" / "common"
+
+        self.set_dataroot('sb_ex_common', dr_path)
+
+        files = [
+            "verilog/umiparam.sv"
+        ]
+
+        deps = [
+            Endpoint()
+        ]
+
+        with self.active_fileset('rtl'):
+            self.set_topmodule(top_module)
+            self.add_depfileset(SwitchboardSim())
+            for item in files:
+                self.add_file(item)
+            for item in deps:
+                self.add_depfileset(item)
+
+        with self.active_fileset('verilator'):
+            self.set_topmodule(top_module)
+            self.add_depfileset(self, "rtl")
+
+        with self.active_fileset('icarus'):
+            self.set_topmodule(top_module)
+            self.add_depfileset(self, "rtl")
 
 
 if __name__ == '__main__':

examples/umiparam/test.py

@@ -5,12 +5,19 @@
 # Copyright (c) 2024 Zero ASIC Corporation
 # This code is licensed under Apache License 2.0 (see LICENSE for details)
 
-from umi import sumi
 import numpy as np
 
+from umi.sumi import Endpoint
+
+from siliconcompiler import Design
+
 from switchboard import SbDut
+from switchboard import sb_path
+from switchboard.verilog.sim.switchboard_sim import SwitchboardSim
 
 from pathlib import Path
+
+
 THIS_DIR = Path(__file__).resolve().parent
 
 
@@ -25,6 +32,42 @@ def main():
     assert value == 42
 
 
+class UmiParam(Design):
+
+    def __init__(self):
+        super().__init__("umiparam")
+
+        top_module = "umiparam"
+
+        dr_path = sb_path() / ".." / "examples" / "common"
+
+        self.set_dataroot('sb_ex_common', dr_path)
+
+        files = [
+            "verilog/umiparam.sv"
+        ]
+
+        deps = [
+            Endpoint()
+        ]
+
+        with self.active_fileset('rtl'):
+            self.set_topmodule(top_module)
+            self.add_depfileset(SwitchboardSim())
+            for item in files:
+                self.add_file(item)
+            for item in deps:
+                self.add_depfileset(item)
+
+        with self.active_fileset('verilator'):
+            self.set_topmodule(top_module)
+            self.add_depfileset(self, "rtl")
+
+        with self.active_fileset('icarus'):
+            self.set_topmodule(top_module)
+            self.add_depfileset(self, "rtl")
+
+
 def build_testbench():
     dw = 32
     aw = 64
@@ -44,12 +87,14 @@ def build_testbench():
 
     resets = ['nreset']
 
-    dut = SbDut('umiparam', cmdline=True, autowrap=True, parameters=parameters,
-        interfaces=interfaces, resets=resets)
-
-    dut.use(sumi)
-
-    dut.input('../common/verilog/umiparam.sv')
+    dut = SbDut(
+        UmiParam(),
+        cmdline=True,
+        autowrap=True,
+        parameters=parameters,
+        interfaces=interfaces,
+        resets=resets
+    )
 
     dut.build()
 

examples/umiram/test.py

@@ -10,7 +10,9 @@
 import numpy as np
 from pathlib import Path
 from switchboard import SbDut, UmiTxRx, binary_run
-from umi import sumi
+
+from umiram import UmiRam
+
 
 THIS_DIR = Path(__file__).resolve().parent
 
@@ -89,12 +91,7 @@ def build_testbench():
         help='Programming language used for the test stimulus.')
     }
 
-    dut = SbDut('testbench', cmdline=True, trace_type='fst', extra_args=extra_args)
-
-    dut.input('testbench.sv')
-    dut.input(THIS_DIR.parent / 'common' / 'verilog' / 'umiram.sv')
-
-    dut.use(sumi)
+    dut = SbDut(UmiRam(), cmdline=True, trace_type='fst', extra_args=extra_args)
 
     dut.build()