Missing x86 mnemonics and registers (self-hosted backend encoder)

[Arnau478]

There are some assembly instruction mnemonics missing on the x86 backend, specially some CPL0 instructions like cli, sti, wrmsr, rdmsr, hlt, ltr, lidt, iretq, hlt... There are some registers missing too, namely the control registers (cr0, cr2, and so on).

[sfiedler0]

The int mnemonic is missing too…

It throws an interrupt (for example int $1) and can be really good for testing interrupt handlers in the kernel. So it would be nice if that could be implemented.

I just noticed, inb and outb (and as far as I can see all other ins and outs) are missing, so debug logging to UART does not work.