Prepare first release candidate

.editorconfig

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+root = true
+
+[*]
+charset = utf-8
+# end_of_line = lf
+insert_final_newline = true
+trim_trailing_whitespace = true
+indent_style = tab
+indent_size = 2
+tab_width = 2
+
+
+[*.py]
+indent_style = tab
+indent_size = 2
+
+[*.{yml,yaml}]
+indent_style = space
+indent_size = 2
+
+[*.{json,ini}]
+indent_style = tab
+indent_size = 2
+
+[*.md]
+trim_trailing_whitespace = false
+
+[*.rst]
+indent_style = space
+indent_size = 3

.gitignore

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-/temp
+# Python cache and object files
+__pycache__/
+*.py[cod]
+
+# Sphinx documentation
+/doc/_build
+
+# PyCharm project
+/.idea/workspace.xml
+
+# Temperary generated outputs from scripts
+/temp

.readthedocs.yml

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+version: 2
+
+submodules:
+  include: []
+
+build:
+  image: latest
+
+python:
+  version: 3.8
+  install:
+    - requirements: doc/requirements.txt
+
+sphinx:
+  builder: html
+  configuration: doc/conf.py
+
+formats:
+  - pdf
+#  - htmlzip
+#  - epub

IO/Cages.vhdl

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+-- EMACS settings: -*-	tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:         Patrick Lehmann
+--
+-- Package:         VHDL-2019 interface descriptions for cages
+--
+-- Description:
+-- -------------------------------------
+-- This package
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2020 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+
+use     work.Common.all;
+use     work.I2C.all;
+
+
+-- Signal name mappings
+--
+--
+package Cages is
+	-- SFP/SFP+
+	type SFP_Interface is record
+		ModuleAbsent    : std_logic;
+
+		I2C             : I2C_PCB_Interface;
+
+		TX_Disable      : std_logic;
+		TX_Fault        : std_logic;
+		RX_LossOfSignal : std_logic;
+
+		TX              : Differatial_Interface;
+		RX              : Differatial_Interface;
+	end record;
+
+	view SFP_ICView of SFP_Interface is
+		ModuleAbsent    : in;
+
+		I2C             : view I2C_PCB_View;
+
+		TX_Disable      : out;
+		TX_Fault        : in;
+		RX_LossOfSignal : in;
+
+		TX              : view Differatial_OutView;
+		RX              : view Differatial_InView;
+	end view;
+	alias SFP_CageView is SFP_ICView'converse;
+
+	type SFP_Interface_Vector is
+		array(natural range <>)
+		of SFP_Interface;
+
+
+	-- QSFP/QSFP+/QSFP28/QSFP28+
+	type QSFP_Interface is record
+		ModuleSelect_n  : std_logic;
+		ModulePresent_n : std_logic;
+		LowPowerMode    : std_logic;
+
+		Reset_n         : std_logic;
+		I2C             : I2C_PCB_Interface;
+		Interrupt_n     : std_logic;
+
+		TX              : Differatial_Interface_Vector(3 downto 0);
+		RX              : Differatial_Interface_Vector(3 downto 0);
+	end record;
+
+	view QSFP_ICView of QSFP_Interface is
+		ModuleSelect_n  : out;
+		ModulePresent_n : in;
+		LowPowerMode    : out;
+
+		Reset_n         : out;
+		I2C             : view I2C_PCB_View;
+		Interrupt_n     : in;
+
+		TX              : view ( Differatial_OutView );
+		RX              : view ( Differatial_InView );
+	end view;
+	alias QSFP_CageView is QSFP_ICView'converse;
+
+	type QSFP_Interface_Vector is
+		array(natural range <>)
+		of QSFP_Interface;
+end package;

IO/Common.vhdl

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+-- EMACS settings: -*-	tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:         Patrick Lehmann
+--
+-- Package:         VHDL-2019 common interface descriptions
+--
+-- Description:
+-- -------------------------------------
+-- This package 
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2020 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+
+package Common is
+	-- Differential signaling (DS or LVDS)
+	type Differatial_Interface is record
+		P : std_logic;
+		N : std_logic;
+	end record;
+
+	alias LVDS_Interface        is Differatial_Interface;
+
+	view Differatial_OutView of Differatial_Interface is
+		P : out;
+		N : out;
+	end view;
+	alias Differatial_InView is Differatial_OutView'converse;
+
+	alias LVDS_OutView is Differatial_OutView;
+	alias LVDS_InView  is Differatial_InView;
+
+	type Differatial_Interface_Vector is
+		array(natural range <>)
+		of Differatial_Interface;
+
+	alias LVDS_Interface_Vector is Differatial_Interface;
+
+
+	-- Transceiver lanes with differential signaling
+	type DifferentialLane_Interface is record
+		TX : Differatial_Interface;
+		RX : Differatial_Interface;
+	end record;
+
+	view DifferentialLane_TransmitterView of DifferentialLane_Interface is
+		TX : view Differatial_OutView;
+		RX : view Differatial_InView;
+	end view;
+
+	type DifferentialLane_Interface_Vector is
+		array(natural range <>)
+		of DifferentialLane_Interface;
+
+	alias LVDSLane_Interface_Vector is DifferentialLane_Interface_Vector;
+
+
+	-- Tristate (3-state) interface
+	type Tristate_Interface is record
+		I : std_logic;      -- Input
+		O : std_logic;      -- Output
+		T : std_logic;      -- Tristate / OutputEnable_n
+	end record;
+
+	view Tristate_OutView of Tristate_Interface is
+		I : in;
+		O : out;
+		T : out;
+	end view;
+	alias Tristate_InView is Tristate_OutView'converse;
+
+	type Tristate_Interface_Vector is
+		array(natural range <>)
+		of Tristate_Interface;
+end package;

IO/I2C.vhdl

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+-- EMACS settings: -*-	tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:         Patrick Lehmann
+--
+-- Package:         VHDL-2019 I²C interface descriptions
+--
+-- Description:
+-- -------------------------------------
+-- This package 
+--
+--   Interface name:    I2C (Inter-Integrated Circuit)
+--   Alternative names: Two-Wire-Interface (TWI)
+--   Can be reused for: PMBus, SMBus
+--   Developed by:      Philips / NXP Semiconductor
+--   Standard/Manual:   http://www.nxp.com/documents/user_manual/UM10204.pdf
+--   Further links:     https://en.wikipedia.org/wiki/I%C2%B2C
+--
+-- License:
+-- =============================================================================
+-- Copyright 2016-2020 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+
+use     work.Common.all;
+
+-- Signal name mappings
+-- SCL -> Serial Clock
+-- SDA -> Serial Data
+package I2C is
+	-- Chip external interface (PCB level)
+	type I2C_PCB_Interface is record
+		SCL : std_logic;
+		SDA : std_logic;
+	end record;
+
+	view I2C_PCB_View of I2C_PCB_Interface is
+		SCL : inout;
+		SDA : inout;
+	end view;
+
+	type I2C_PCB_Interface_vector is
+		array(natural range <>)
+		of I2C_PCB_Interface;
+
+
+	-- Chip internal interface, not supporting bidirectional signals (fabric level)
+	type I2C_Interface is record
+		SCL  : Tristate_Interface;
+		SDA  : Tristate_Interface;
+	end record;
+
+	view I2C_ControllerView of I2C_Interface is
+		SCL : view Tristate_OutView;
+		SDA : view Tristate_OutView;
+	end view;
+	alias I2C_IOBView is I2C_ControllerView'converse;
+
+	type I2C_Interface_Vector is array(natural range <>) of I2C_Interface;
+
+end package;