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Some PoC.arith tests converted to OSVVM
2 parents 3b99b32 + d5617f3 commit 62ee0ee

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‎tb/arith/RunAllTests.pro‎

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# =============================================================================
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# Authors: Jonas Schreiner
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# Gustavo Martin
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#
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# License:
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# =============================================================================
@@ -23,3 +24,7 @@ TestSuite PoC.arith
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library tb_arith
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include ./prng/RunAllTests.pro
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include ./prefix_and/RunAllTests.pro
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include ./prefix_or/RunAllTests.pro
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include ./addw/RunAllTests.pro
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include ./counter_bcd/RunAllTests.pro

‎tb/arith/addw/RunAllTests.pro‎

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# =============================================================================
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# Authors:
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# Gustavo Martin
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#
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# License:
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# =============================================================================
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# Copyright 2025-2025 The PoC-Library Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# =============================================================================
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analyze arith_addw_TestController_pkg.vhdl
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analyze arith_addw_TestController.vhdl
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analyze arith_addw_TestHarness.vhdl
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RunTest arith_addw_Simple.vhdl

‎tb/arith/addw/arith_addw_Simple.vhdl‎

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-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
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-- vim: tabstop=2:shiftwidth=2:noexpandtab
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-- kate: tab-width 2; replace-tabs off; indent-width 2;
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-- =============================================================================
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-- Authors: Thomas B. Preusser
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-- Gustavo Martin
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--
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-- Entity: arith_addw_Simple
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--
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-- Description:
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-- -------------------------------------
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-- Simple OSVVM test for arith_addw
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 The PoC-Library Authors
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library osvvm;
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context osvvm.OsvvmContext;
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library PoC;
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use PoC.strings.all;
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use PoC.physical.all;
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use PoC.arith.all;
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use work.arith_addw_TestController_pkg.all;
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architecture Simple of arith_addw_TestController is
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signal TestDone : integer_barrier := 1;
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constant TCID : AlertLogIDType := NewID("AddWTest");
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constant TPERIOD_CLOCK : time := 10 ns;
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begin
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ControlProc: process
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constant ProcID : AlertLogIDType := NewID("ControlProc", TCID);
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constant TIMEOUT : time := 10 ms;
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begin
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SetTestName("arith_addw_Simple");
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SetLogEnable(PASSED, FALSE);
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SetLogEnable(INFO, FALSE);
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SetLogEnable(DEBUG, FALSE);
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wait for 0 ns; wait for 0 ns;
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TranscriptOpen;
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SetTranscriptMirror(TRUE);
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wait until Reset = '0';
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ClearAlerts;
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WaitForBarrier(TestDone, TIMEOUT);
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AlertIf(ProcID, now >= TIMEOUT, "Test finished due to timeout");
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AlertIf(ProcID, GetAffirmCount < 1, "Test is not Self-Checking");
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EndOfTestReports(ReportAll => TRUE);
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std.env.stop;
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end process;
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CheckerProc: process
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constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID);
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variable ai, bi : integer;
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variable expected : natural;
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variable actual_sum : unsigned(9 downto 0);
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begin
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wait until Reset = '0';
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WaitForClock(Clock);
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for i in 0 to 2**9-1 loop
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a <= std_logic_vector(to_unsigned(i, 9));
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for j in 0 to 2**9-1 loop
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b <= std_logic_vector(to_unsigned(j, 9));
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cin <= '0';
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WaitForClock(Clock);
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for arch in tArch loop
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for skip in tSkipping loop
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-- Test with P_INCLUSIVE = false
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expected := (i + j) mod 2**10;
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actual_sum := unsigned(cout(arch, skip, false) & s(arch, skip, false));
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AffirmIf(ProcID, expected = to_integer(actual_sum),
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"Output Error: " & integer'image(i) & "+" & integer'image(j) &
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" arch=" & tArch'image(arch) & " skip=" & tSkipping'image(skip) & " incl=false"
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);
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-- Test with P_INCLUSIVE = true
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actual_sum := unsigned(cout(arch, skip, true) & s(arch, skip, true));
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AffirmIf(ProcID, expected = to_integer(actual_sum),
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"Output Error: " & integer'image(i) & "+" & integer'image(j) &
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" arch=" & tArch'image(arch) & " skip=" & tSkipping'image(skip) & " incl=true"
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);
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end loop;
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end loop;
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cin <= '1';
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WaitForClock(Clock);
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for arch in tArch loop
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for skip in tSkipping loop
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-- Test with P_INCLUSIVE = false
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expected := (i + j + 1) mod 2**10;
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actual_sum := unsigned(cout(arch, skip, false) & s(arch, skip, false));
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AffirmIf(ProcID, expected = to_integer(actual_sum),
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"Output Error with carry: " & integer'image(i) & "+" & integer'image(j) & "+1" &
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" arch=" & tArch'image(arch) & " skip=" & tSkipping'image(skip) & " incl=false"
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);
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-- Test with P_INCLUSIVE = true
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actual_sum := unsigned(cout(arch, skip, true) & s(arch, skip, true));
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AffirmIf(ProcID, expected = to_integer(actual_sum),
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"Output Error with carry: " & integer'image(i) & "+" & integer'image(j) & "+1" &
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" arch=" & tArch'image(arch) & " skip=" & tSkipping'image(skip) & " incl=true"
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);
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end loop;
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end loop;
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end loop;
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end loop;
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WaitForBarrier(TestDone);
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wait;
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end process;
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end architecture;
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configuration arith_addw_Simple of arith_addw_TestHarness is
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for TestHarness
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for TestCtrl: arith_addw_TestController
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use entity work.arith_addw_TestController(Simple);
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end for;
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end for;
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end configuration;

‎tb/arith/addw/arith_addw_TestController.vhdl‎

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-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
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-- vim: tabstop=2:shiftwidth=2:noexpandtab
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-- kate: tab-width 2; replace-tabs off; indent-width 2;
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-- =============================================================================
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-- Authors: Thomas B. Preusser
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-- Gustavo Martin
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--
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-- Entity: arith_addw_TestController
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--
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-- Description:
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-- -------------------------------------
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-- Test controller for arith_addw
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 The PoC-Library Authors
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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library osvvm;
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context osvvm.OsvvmContext;
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library PoC;
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use PoC.arith.all;
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use work.arith_addw_TestController_pkg.all;
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entity arith_addw_TestController is
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port (
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Clock : in std_logic;
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Reset : in std_logic;
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-- DUT ports (arrays for all variants)
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a : out word;
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b : out word;
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cin : out std_logic;
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s : in word_vector;
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cout : in carry_vector
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);
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end entity;

‎tb/arith/addw/arith_addw_TestController_pkg.vhdl‎

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-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
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-- vim: tabstop=2:shiftwidth=2:noexpandtab
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-- kate: tab-width 2; replace-tabs off; indent-width 2;
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-- =============================================================================
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-- Authors: Thomas B. Preusser
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-- Gustavo Martin
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--
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-- Entity: arith_addw_TestController_pkg
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--
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-- Description:
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-- -------------------------------------
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-- Test controller package for arith_addw
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 The PoC-Library Authors
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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library osvvm;
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context osvvm.OsvvmContext;
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library PoC;
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use PoC.arith.all;
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package arith_addw_TestController_pkg is
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constant N : positive := 9;
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constant K : positive := 2;
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subtype tArch_test is tArch;
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subtype tSkip_test is tSkipping;
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subtype word is std_logic_vector(N-1 downto 0);
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type word_vector is array(tArch_test, tSkip_test, boolean) of word;
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type carry_vector is array(tArch_test, tSkip_test, boolean) of std_logic;
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end package arith_addw_TestController_pkg;

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