AIE: Update 04 packet_aie/sw/Makefile to resolve syntax issue; rm 02/…

…03/04 description of ES board

* update from xclbin to xsa

* update Makefile for syntax of copyright

* update README to remove ES

* update graph.cpp

Co-authored-by: brucey <[email protected]>

AI_Engine_Development/Feature_Tutorials/02-using-gmio/README.md

@@ -24,12 +24,6 @@ Before starting this tutorial, run the following steps:
 3.	Set up your IMAGE to point to xilinx-versal-common-v2022.1/Image.
 4. Set up your `PLATFORM_REPO_PATHS` environment variable based upon where you downloaded the platform.
 
-> **Note**: This tutorial targets the [VCK190 ES board](https://www.xilinx.com/products/boards-and-kits/vck190.html). This board is currently available via early access. If you have already purchased this board, download the necessary files from the lounge and ensure you have the correct licenses installed. If you do not have a board and ES license, contact your Xilinx sales contact.
-
-To target the VCK190 production board, modify `PLATFORM` variable in the `Makefile`(s) to:
-
-    PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vck190_base_202120_1/xilinx_vck190_base_202120_1.xpfm
-
 ## Objectives
 
 After completing this tutorial, you will be able to:

AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/README.md

@@ -24,14 +24,6 @@ Before starting this tutorial run the steps below:
 3. Set up your IMAGE to point to `xilinx-versal-common-v2022.1/Image`.
 4. Set up your `PLATFORM_REPO_PATHS` environment variable based upon where you downloaded the platform.
 
-> **Note**: This tutorial targets the [VCK190 ES board](https://www.xilinx.com/products/boards-and-kits/vck190.html). This board is currently available via early access. If you have already purchased this board, download the necessary files from the lounge and ensure you have the correct licenses installed. If you do not have a board and ES license, contact your Xilinx sales contact.
-
-To target the VCK190 production board, modify the `PLATFORM` variable in the `Makefile`(s) to:
-
-  ```
-  PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vck190_base_202120_1/xilinx_vck190_base_202120_1.xpfm
-  ```
-
 ## Objectives
 
 After completing this tutorial, you will be able to:

AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step1/aie/graph.cpp

@@ -31,5 +31,6 @@ int main(int argc, char ** argv) {
   gr.update(gr.trigger,100);
 
   gr.end();
+  return 0;
 };
 #endif

AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step2/aie/graph.cpp

@@ -30,4 +30,5 @@ int main(int argc, char ** argv) {
   gr.run(2);
 
   gr.end();
+  return 0;
 };

AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step3/aie/graph.cpp

@@ -28,6 +28,7 @@ int main(int argc, char **argv)
   gr.update(gr.coefficients, wide_filter, 12);
   gr.run(16);
   gr.end();
+  return 0;
 };
 #endif
 

AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step4/aie/graph.cpp

@@ -31,6 +31,7 @@ int main(int argc, char **argv)
   gr.run(16); // start PL kernel & AIE kernel
 
   gr.end();
+  return 0;
 };
 #endif
 

AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step5/aie/graph.cpp

@@ -51,6 +51,7 @@ int main(int argc, char **argv)
   std::cout<<std::endl;
 
   gr.end();
+  return 0;
 };
 #endif
 

AI_Engine_Development/Feature_Tutorials/04-packet-switching/README.md

@@ -26,11 +26,6 @@ Before starting this tutorial run the following steps.
 3. Set up your IMAGE to point to `xilinx-versal-common-v2022.1/Image`.
 4. Set up your `PLATFORM_REPO_PATHS` environment variable based upon where you downloaded the platform.
 
-This tutorial targets the VCK190 ES board (see https://www.xilinx.com/products/boards-and-kits/vck190.html). This board is currently available via early access. If you have already purchased this board, download the necessary files from the lounge and ensure you have the correct licenses installed. If you do not have a board and ES license please contact your Xilinx sales contact.
-
-To target the VCK190 production board, modify `PLATFORM` variable in the `Makefile`(s) to:
-
-    PLATFORM = ${PLATFORM_REPO_PATHS}/xilinx_vck190_base_202120_1/xilinx_vck190_base_202120_1.xpfm
 
 ## Objectives
 After completing this tutorial, you will be able to:

AI_Engine_Development/Feature_Tutorials/04-packet-switching/pktstream_aie/sw/Makefile

@@ -1,5 +1,4 @@
-#
-© Copyright 2020-2021 Xilinx, Inc.
+#© Copyright 2020-2021 Xilinx, Inc.
 #Licensed under the Apache License, Version 2.0 (the "License");
 #you may not use this file except in compliance with the License.
 #You may obtain a copy of the License at

AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_aie_kernel.md

@@ -73,7 +73,7 @@ Change the working directory to `window_aie`. The example graph code is in `aie/
 	  }
 	};
 
-This is a graph with a 4:1 splitter `pktsplit<4>` and 1:4 merger `pktmerge<4>`. Note that the connection type for `pktsplit` and `pktmerge` is `adf::pktstream`. The input port `in` is first connected to the `pktsplit`, and `pktsplit` switches the packets to different AI Engine kernels. The outputs of AI Engine kernels are connected to the `pktmerge`, and `pktmerge` generates packet headers for those packets automatically and outputs them through output port, `out`. 
+This is a graph with a 1:4 splitter `pktsplit<4>` and 1:1 merger `pktmerge<4>`. Note that the connection type for `pktsplit` and `pktmerge` is `adf::pktstream`. The input port `in` is first connected to the `pktsplit`, and `pktsplit` switches the packets to different AI Engine kernels. The outputs of AI Engine kernels are connected to the `pktmerge`, and `pktmerge` generates packet headers for those packets automatically and outputs them through output port, `out`. 
 
 Run the make command `make aie` to compile the graph. Then open the compiled summary with the Vitis™ analyzer using the command `vitis_analyzer ./Work/graph.aiecompile_summary`. Then click the `Graph` tab in the Vitis analyzer. The graph of the design is shown as follows.
 

AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/README.md

@@ -45,8 +45,6 @@ Before starting this tutorial, complete the following steps:
 2. Set up your `ROOTFS` and `IMAGE` to point to the `xilinx-versal-common-v2022.1` directory.
 3. Set up your `PLATFORM_REPO_PATHS` environment variable based upon where you downloaded the platform.
 
-This tutorial targets the VCK190 ES board (see https://www.xilinx.com/products/boards-and-kits/vck190.html). This board is currently available via early access. If you have already purchased this board, download the necessary files from the lounge and ensure you have the correct licenses installed. If you do not have a board and ES license please contact your Xilinx sales contact.
-
 ### Objectives
 
 After completing the tutorial, you should be able to:

AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/testcase_dmafifo_opt/aie/graph.cpp

@@ -34,6 +34,7 @@ int main(int argc, char **argv)
 	event::stop_profiling(handle);
 	double throughput = (double)total_bytes / (cycle_count * 1e-3); 
 	printf("Throughput of the graph: %f MB/s\n",throughput);
+	return 0;
 };
 #endif
 

AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/testcase_nofifo_hang/aie/graph.cpp

@@ -21,6 +21,7 @@ int main(int argc, char **argv)
   gr.init();
   gr.run(4);
   gr.wait(10000);
+  return 0;
 };
 #endif
 

AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/testcase_ssfifo/aie/graph.cpp

@@ -34,6 +34,7 @@ int main(int argc, char **argv)
 	event::stop_profiling(handle);
 	double throughput = (double)total_bytes / (cycle_count * 1e-3); 
 	printf("Throughput of the graph: %f MB/s\n",throughput);
+	return 0;
 };
 #endif