Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[AIE2/2P] Fix DONE latency at region end. #345

Open
wants to merge 1 commit into
base: aie-public
Choose a base branch
from
+62 −0
Open

[AIE2/2P] Fix DONE latency at region end. #345

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions llvm/lib/Target/AIE/AIE2InstrInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1165,6 +1165,15 @@ bool AIE2InstrInfo::isLock(unsigned Opc) const {
return false;
}

bool AIE2InstrInfo::isDone(unsigned Opc) const { return Opc == AIE2::DONE; }

unsigned AIE2InstrInfo::getImplicitLatency(const MachineInstr &MI) const {
if (isDone(MI.getOpcode()))
return 6;

return 0;
}

bool AIE2InstrInfo::isDelayedSchedBarrier(const MachineInstr &MI) const {
return MI.getOpcode() == AIE2::DelayedSchedBarrier;
}
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AIE/AIE2InstrInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,8 @@ class AIE2InstrInfo : public AIE2GenInstrInfo {
unsigned getGenericBroadcastVectorOpcode() const override;
unsigned getCycleSeparatorOpcode() const override;
bool isLock(unsigned Opc) const override;
bool isDone(unsigned Opc) const override;
unsigned getImplicitLatency(const MachineInstr &) const override;
bool isDelayedSchedBarrier(const MachineInstr &MI) const override;
bool isSchedBarrier(const MachineInstr &MI) const override;

Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseInstrInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -176,6 +176,13 @@ struct AIEBaseInstrInfo : public TargetInstrInfo {
}
/// Check whether Opc represents a lock instruction
virtual bool isLock(unsigned Opc) const { return false; }

/// Check whether Opc represents a DONE instruction
virtual bool isDone(unsigned Opc) const { return false; }
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit: I hope no one needs to call this from outside. This one could go and instances could be private or inlined.

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think we can have a design where we need just one method to be reimplemented. Something like:

virtual std::optional<unsigned> getDoneLatency(...)

In this case, we can have a base implementation for getImplicitLatency that can be reimplemented by the target only if needed.

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@andcarminati, The idea was to have a more generic name excluding 'Done'. It's basically an extra latency that can be given to the exit edge. But yes, we would only have one generic method that fills it in.

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Hi, my idea is to avoid encode the latency knowledge separately. If we have a new done, we have two places to change.


/// Get "implicit" latency for special instructions.
virtual unsigned getImplicitLatency(const MachineInstr &) const { return 0; }
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can you document what that means?


/// Check whether this is a delayed scheduling barrier induced from
/// a preceding instruction with delay slots.
virtual bool isDelayedSchedBarrier(const MachineInstr &) const {
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/AIE/AIEBaseSubtarget.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -280,6 +280,10 @@ class RegionEndEdges : public ScheduleDAGMutation {
EdgeLatency = DelaySlots + 1;
}

// "Implicit" latency for special instructions.
const unsigned ImplicitLatency = TII->getImplicitLatency(MI);
EdgeLatency = std::max(EdgeLatency, ImplicitLatency);
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

FYI @mludevid you might have done something similar when working on semaphores.


// Between writing ZOL Registers (lc, le, ls) and the end of the loop,
// there must be a minimum distance. This is ultimately padded out by the
// alignment pass using bundle elongation, but this needs to have enough
Expand Down
9 changes: 9 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1208,6 +1208,15 @@ bool AIE2PInstrInfo::isLock(unsigned Opc) const {
return false;
}

bool AIE2PInstrInfo::isDone(unsigned Opc) const { return Opc == AIE2P::DONE; }

unsigned AIE2PInstrInfo::getImplicitLatency(const MachineInstr &MI) const {
if (isDone(MI.getOpcode()))
return 6;

return 0;
}

bool AIE2PInstrInfo::isDelayedSchedBarrier(const MachineInstr &MI) const {
return MI.getOpcode() == AIE2P::DelayedSchedBarrier;
}
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,8 @@ class AIE2PInstrInfo : public AIE2PGenInstrInfo {
unsigned getGenericVShiftOpcode() const override;
unsigned getGenericExtractSubvectorOpcode() const override;
bool isLock(unsigned Opc) const override;
bool isDone(unsigned Opc) const override;
unsigned getImplicitLatency(const MachineInstr &) const override;
bool isDelayedSchedBarrier(const MachineInstr &MI) const override;
bool isSchedBarrier(const MachineInstr &MI) const override;

Expand Down
29 changes: 29 additions & 0 deletions llvm/test/CodeGen/AIE/schedule/done.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
#
# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
# See https://llvm.org/LICENSE.txt for license information.
# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#
# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates

# RUN: llc -march=aie2 --issue-limit=6 --aie-bottomup-cycles=0 -run-pass=postmisched %s -o - | FileCheck %s
# RUN: llc -march=aie2p --issue-limit=6 --aie-bottomup-cycles=0 -run-pass=postmisched %s -o - | FileCheck %s

# Check 6 cycle latency at region end.
---
name: done
body: |
bb.0.entry:
; CHECK-LABEL: name: done
; CHECK: SCHED_BARRIER
; CHECK-NEXT: DONE
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP
; CHECK-NEXT: SCHED_BARRIER
SCHED_BARRIER
DONE
SCHED_BARRIER
...