Air/src/cpu by this-vishalsingh · Pull Request #23 · ZippelLabs/ZP1

Commits on Dec 12, 2025

feat: implement `load_byte_constraint` with byte decomposition, selection, and sign extension.
Shivannsh
committed
feat: implement load_halfword_constraint with sign extension and add tests
Shivannsh
committed
feat: Refactor `load_word_constraint` to operate on 32-bit word limbs and return multiple constraints.
Shivannsh
committed

Commits on Dec 13, 2025

feat: Implement `load_byte_unsigned_constraint` constraint with byte decomposition, selection, and zero extension, and add a full test.
Shivannsh
committed
feat: correctly implement `load_halfword_unsigned_constraint` with full logic and added a dedicated test.
Shivannsh
committed
feat: implement full `store_byte_constraint` logic with byte decomposition, offset verification, and memory update, and add a comprehensive test.
Shivannsh
committed
feat: Implement `store_halfword_constraint` with detailed halfword decomposition and update logic, and add a new test case.
Shivannsh
committed
refactor: Update `store_word_constraint` to use two M31 limbs for word values and return a vector of constraints.
Shivannsh
committed
refactor: reimplement `word_alignment_constraint` to use bit decomposition witnesses and return multiple constraints, and update its test.
Shivannsh
committed
feat: implement `halfword_alignment_constraint` using witness values and add comprehensive tests for alignment.
Shivannsh
committed
feat: Implement full 64-bit MUL constraint verification using 16-bit limbs and carries.
Shivannsh
committed
feat: Implement `mulh_constraint` with correct signed multiplication logic, including carries, signs, and overflow factor, and update its test.
Shivannsh
committed
feat: reimplement `mulhsu_constraint` for signed-unsigned high multiplication and add its test.`
Shivannsh
committed
feat: implement `mulhu_constraint` with full unsigned high multiplication logic and update its test, and correct carry calculation in related multiplication tests.
Shivannsh
committed
feat: Add full 32-bit signed division constraints to `div_constraint` with carry witnesses and update tests.
Shivannsh
committed
feat: Implement full 64-bit unsigned division (DIVU) `divu_constraint` using limb arithmetic and carries.
Shivannsh
committed
feat: Implement detailed `rem_constraint` logic by adding witness variables and returning multiple constraints for verification.
Shivannsh
committed
feat: Implement detailed multi-constraint verification for unsigned remainder (REMU) using intermediate product and carry witnesses.
Shivannsh
committed

Commits on Dec 14, 2025

Commits on Dec 15, 2025

Commits on Dec 16, 2025

feat: Refactor `jalr_constraint` to use limb-based register values and correctly implement next PC alignment.
Shivannsh
committed

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Air/src/cpu#23

Air/src/cpu#23
this-vishalsingh wants to merge 24 commits intomainfrom
air/src/cpu

Commits on Dec 12, 2025

feat: implement `load_byte_constraint` with byte decomposition, selection, and sign extension.

feat: implement load_halfword_constraint with sign extension and add tests

feat: Refactor `load_word_constraint` to operate on 32-bit word limbs and return multiple constraints.

Commits on Dec 13, 2025

feat: Implement `load_byte_unsigned_constraint` constraint with byte decomposition, selection, and zero extension, and add a full test.

feat: correctly implement `load_halfword_unsigned_constraint` with full logic and added a dedicated test.

feat: implement full `store_byte_constraint` logic with byte decomposition, offset verification, and memory update, and add a comprehensive test.

feat: Implement `store_halfword_constraint` with detailed halfword decomposition and update logic, and add a new test case.

refactor: Update `store_word_constraint` to use two M31 limbs for word values and return a vector of constraints.

refactor: reimplement `word_alignment_constraint` to use bit decomposition witnesses and return multiple constraints, and update its test.

feat: implement `halfword_alignment_constraint` using witness values and add comprehensive tests for alignment.

feat: Implement full 64-bit MUL constraint verification using 16-bit limbs and carries.

feat: Implement `mulh_constraint` with correct signed multiplication logic, including carries, signs, and overflow factor, and update its test.

feat: reimplement `mulhsu_constraint` for signed-unsigned high multiplication and add its test.`

feat: implement `mulhu_constraint` with full unsigned high multiplication logic and update its test, and correct carry calculation in related multiplication tests.

feat: Add full 32-bit signed division constraints to `div_constraint` with carry witnesses and update tests.

feat: Implement full 64-bit unsigned division (DIVU) `divu_constraint` using limb arithmetic and carries.

feat: Implement detailed `rem_constraint` logic by adding witness variables and returning multiple constraints for verification.

feat: Implement detailed multi-constraint verification for unsigned remainder (REMU) using intermediate product and carry witnesses.

Commits on Dec 14, 2025

refactor: Update `beq_constraint` to use an IsZero gadget for equality checks and return multiple constraints.

refactor: reimplement `bne_constraint` using IsZero gadgets and add a test for the not-taken case.

Commits on Dec 15, 2025

feat: implement full constraint logic for `blt_constraint` and `bge_constraint` signed branch instructions with witness parameters.

feat: Refactor `bltu_constraint` and `bgeu_constraint` to use explicit witnesses for unsigned comparison and return multiple constraints.

refactor: update `jal_constraint` to accept split rd_val limbs and return a vector of constraints.

Commits on Dec 16, 2025

feat: Refactor `jalr_constraint` to use limb-based register values and correctly implement next PC alignment.