Handle vector width (VLEN) for RISCV arches

[cbalint13]

This PR address issue #17625 by making llvm codegen backend aware of RVV VLEN.

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By default this has no impact on anything but the RISCV targets.

• Introduces optional -vector-length parameter for any of llvm targets
• For RISCV infers from LLVM library the appropiate VLEN based on the tvm target specified
• It properly warns on any inference failure with a default value, and suggests the -vector-length usage

Cc: @JieGH , if by chance can get a feedback
Cc: LLVM folks @quic-sanirudh , @srkreddy1238

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Snippet of test function used:

    m = 4
    n = 4 # multiple of int32_lanes   (2)
    k = 4 # multiple of int8_elements (8) (the common axis)

    # network graph
    dat = relay.var("data", shape=(m, k), dtype="uint8")
    weight = relay.var("weight", shape=(n, k), dtype="int8")
    out = relay.nn.dense(dat, weight, out_dtype="int32")

    # convert to relay IR
    f = relay.Function(relay.analysis.free_vars(out), out)
    mod, params = testing.create_workload(f)

Results with default, VLEN = {128,256,512} and without RVV scenarios:

# a generic cpu, but no RVV extension enabled
llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64 -mattr=+64bit,+a,+c,+d,+f,+m
$ riscv64-linux-gnu-objdump -D lib0.o | grep vsetvli
{nothing}

# a generic cpu w/RVV, unknown VLEN in LLVM (defaults to 256 bit, +warning)
llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64 -mattr=+64bit,+a,+c,+d,+f,+m,+v
$ riscv64-linux-gnu-objdump -D lib0.o | grep vsetvli
 a9a:	0c1077d7          	vsetvli	a5,zero,e8,m2,ta,ma
codegen_llvm.cc:193: Warning: LLVM RVV VLEN inference failed, using 256 bits, set -vector-width=XXX to override

# a generic cpu w/RVV, explicit 128 bit for VLEN
llvm -device=riscv_cpu -vector-width=128 -mtriple=riscv64-linux-gnu -mcpu=generic-rv64 -mattr=+64bit,+a,+c,+d,+f,+m,+v
$ riscv64-linux-gnu-objdump -D lib0.o | grep vsetvli
 a96:	0c007557          	vsetvli	a0,zero,e8,m1,ta,ma

# a generic cpu w/RVV, explicit 256 bit for VLEN
llvm -device=riscv_cpu -vector-width=256 -mtriple=riscv64-linux-gnu -mcpu=generic-rv64 -mattr=+64bit,+a,+c,+d,+f,+m,+v
$ riscv64-linux-gnu-objdump -D lib0.o | grep vsetvli
 a9a:	0c1077d7          	vsetvli	a5,zero,e8,m2,ta,ma

# a spacemit-x60 cpu, LLVM-20 infers that this has RVV unit with VLEN 256
llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=spacemit-x60
$ riscv64-linux-gnu-objdump -D lib0.o | grep vsetvli
 a3c:	0c107757          	vsetvli	a4,zero,e8,m2,ta,ma

# a generic cpu w/RVV, explicit 512 bit for VLEN
llvm -device=riscv_cpu -vector-width=512 -mtriple=riscv64-linux-gnu -mcpu=generic-rv64 -mattr=+64bit,+a,+c,+d,+f,+m,+v
$ riscv64-linux-gnu-objdump -D lib0.o | grep vsetvli
 b08:	04307557          	vsetvli	a0,zero,e8,m8,ta,mu

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Tests here were conducted against LLVM = 20 .
Compilation were tested against LLVM = {10,11,12,13,14,15,16,17,18,19,20} , also revisiting issue #16708 .