feat: the great FP_ removal + FP_FLIP_SITES

To make variable names more consistent, IO and PDN variables have been renamed to drop FP_.

Changelog.md

@@ -28,6 +28,10 @@
   * `PDN_OBSTRUCTIONS` and `ROUTING_OBSTRUCTIONS` are now lists of tuples
     instead of variable-length Tcl-style lists (AKA: strings).
 
+* `Odb.CustomIOPlacement`
+
+  * All variables prefixed `FP_IO_` have been renamed, now prefixed `IO_PIN_`.
+
 * `OpenROAD.*`
 
   * Added `PNR_CORNERS`. An override for `DEFAULT_CORNER` for PnR steps except
@@ -75,9 +79,24 @@
   * Creates three reports to help verify that the RC values used for estimation
     are set correctly.
 
+* `OpenROAD.Floorplan`
+
+  * Added `FP_FLIP_SITES`: allows sites in floorplans to be flipped. Useful in
+    niche alignment scenarios where single-height cells have ground at the south
+    side and double-height cells have power at the south side, causing a short.
+    In that situation, flipping the sites for single-height cells resolves the
+    issue.
+
+* `OpenROAD.GeneratePDN`
+
+  * All variables prefixed `FP_PDN_` have been renamed to be prefixed simply
+    `PDN`. Backwards compatibility wrapper code has been added for `PDN_CFG`
+    files.
+
 * `OpenROAD.GlobalPlacement`
 
   * Added optional variable `PL_ROUTABILITY_MAX_DENSITY_PCT`
+
   * Added optional variable `PL_KEEP_RESIZE_BELOW_OVERFLOW`
 
   * Corrected `GPL_CELL_PADDING` to be an integer.

docs/source/reference/pin_placement_cfg.md

@@ -1,7 +1,7 @@
 # Pin Placer Configuration Files
 
 If you're using the step {step}`Odb.CustomIOPlacement`
-the variable `FP_PIN_ORDER_CFG` asks you to create a `.cfg` file that can be used
+the variable `IO_PIN_ORDER_CFG` asks you to create a `.cfg` file that can be used
 to configure this placement step.
 
 ## Parsing and Grammar

docs/source/usage/caravel/index.md

@@ -145,7 +145,7 @@ ______________________________________________________________________
 ```json
 {
     "DESIGN_NAME": "aes_wb_wrapper",
-    "FP_PDN_MULTILAYER": false,
+    "PDN_MULTILAYER": false,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_PERIOD": 25,
     "VERILOG_FILES": [
@@ -175,7 +175,7 @@ This is a basic configuration file which has only these variables:
 * {var}`OpenROAD.Floorplan::FP_CORE_UTIL`: The core utilization. Typical values
   for the core utilization range from 25% to 60%. 40% is a good starting value -
   we can adjust it later if we need to (i.e. one of the tools complains.)
-* {var}`OpenROAD.GeneratePDN::FP_PDN_MULTILAYER`: We set this to `false` as we
+* {var}`OpenROAD.GeneratePDN::PDN_MULTILAYER`: We set this to `false` as we
   are hardening a chip for integration into Caravel. You may review
   {doc}`/usage/pdn` for more information on this.
 
@@ -705,7 +705,7 @@ So, the final `config.json` is as follows:
 ```json
 {
     "DESIGN_NAME": "aes_wb_wrapper",
-    "FP_PDN_MULTILAYER": false,
+    "PDN_MULTILAYER": false,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_PERIOD": 25,
     "VERILOG_FILES": [
@@ -834,13 +834,13 @@ section can be found at the end of the configurations file
         "vssa1",
         "vssa2"
     ],
-    "FP_PDN_CORE_RING": 1,
-    "FP_PDN_CORE_RING_VWIDTH": 3.1,
-    "FP_PDN_CORE_RING_HWIDTH": 3.1,
-    "FP_PDN_CORE_RING_VOFFSET": 12.45,
-    "FP_PDN_CORE_RING_HOFFSET": 12.45,
-    "FP_PDN_CORE_RING_VSPACING": 1.7,
-    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "PDN_CORE_RING": 1,
+    "PDN_CORE_RING_VWIDTH": 3.1,
+    "PDN_CORE_RING_HWIDTH": 3.1,
+    "PDN_CORE_RING_VOFFSET": 12.45,
+    "PDN_CORE_RING_HOFFSET": 12.45,
+    "PDN_CORE_RING_VSPACING": 1.7,
+    "PDN_CORE_RING_HSPACING": 1.7,
     "CLOCK_PORT": "wb_clk_i",
     "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
     "MAGIC_DEF_LABELS": 0,
@@ -1100,14 +1100,14 @@ wbs_.*
 ```
 ````
 
-2. Add the `Odb.CustomIOPlacement::FP_PIN_ORDER_CFG` variable to
+2. Add the `Odb.CustomIOPlacement::IO_PIN_ORDER_CFG` variable to
    `openlane/aes_wb_wrapper/config.json`
 
 ````{dropdown} config.json
 ```json
 {
     "DESIGN_NAME": "aes_wb_wrapper",
-    "FP_PDN_MULTILAYER": false,
+    "PDN_MULTILAYER": false,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_PERIOD": 25,
     "VERILOG_FILES": [
@@ -1129,7 +1129,7 @@ wbs_.*
     "RUN_POST_GRT_DESIGN_REPAIR": true,
     "PNR_SDC_FILE": "dir::pnr.sdc",
     "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
-    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg"
+    "IO_PIN_ORDER_CFG": "dir::pin_order.cfg"
 }
 ```
 ````
@@ -1152,7 +1152,7 @@ wbs_.*
     "RUN_POST_GPL_DESIGN_REPAIR": false,
     "RUN_POST_CTS_RESIZER_TIMING": false,
     "DESIGN_REPAIR_BUFFER_INPUT_PORTS": false,
-    "FP_PDN_ENABLE_RAILS": false,
+    "PDN_ENABLE_RAILS": false,
     "RUN_ANTENNA_REPAIR": false,
     "RUN_FILL_INSERTION": false,
     "RUN_TAP_ENDCAP_INSERTION": false,
@@ -1196,14 +1196,14 @@ wbs_.*
     "PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 VPWR VGND"],
 
     "//": "PDN configurations",
-    "FP_PDN_VOFFSET": 5,
-    "FP_PDN_HOFFSET": 5,
-    "FP_PDN_VWIDTH": 3.1,
-    "FP_PDN_HWIDTH": 3.1,
-    "FP_PDN_VSPACING": 15.5,
-    "FP_PDN_HSPACING": 15.5,
-    "FP_PDN_VPITCH": 180,
-    "FP_PDN_HPITCH": 180,
+    "PDN_VOFFSET": 5,
+    "PDN_HOFFSET": 5,
+    "PDN_VWIDTH": 3.1,
+    "PDN_HWIDTH": 3.1,
+    "PDN_VSPACING": 15.5,
+    "PDN_HSPACING": 15.5,
+    "PDN_VPITCH": 180,
+    "PDN_HPITCH": 180,
     "QUIT_ON_PDN_VIOLATIONS": false,
 
     "//": "Magic variables",
@@ -1228,13 +1228,13 @@ wbs_.*
         "vssa1",
         "vssa2"
     ],
-    "FP_PDN_CORE_RING": 1,
-    "FP_PDN_CORE_RING_VWIDTH": 3.1,
-    "FP_PDN_CORE_RING_HWIDTH": 3.1,
-    "FP_PDN_CORE_RING_VOFFSET": 12.45,
-    "FP_PDN_CORE_RING_HOFFSET": 12.45,
-    "FP_PDN_CORE_RING_VSPACING": 1.7,
-    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "PDN_CORE_RING": 1,
+    "PDN_CORE_RING_VWIDTH": 3.1,
+    "PDN_CORE_RING_HWIDTH": 3.1,
+    "PDN_CORE_RING_VOFFSET": 12.45,
+    "PDN_CORE_RING_HOFFSET": 12.45,
+    "PDN_CORE_RING_VSPACING": 1.7,
+    "PDN_CORE_RING_HSPACING": 1.7,
     "CLOCK_PORT": "wb_clk_i",
     "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
     "MAGIC_DEF_LABELS": 0,
@@ -1373,7 +1373,7 @@ are needed for the `user_project_wrapper`
     "RUN_POST_GPL_DESIGN_REPAIR": true,
     "RUN_POST_CTS_RESIZER_TIMING": true,
     "DESIGN_REPAIR_BUFFER_INPUT_PORTS": true,
-    "FP_PDN_ENABLE_RAILS": true,
+    "PDN_ENABLE_RAILS": true,
     "RUN_ANTENNA_REPAIR": true,
     "RUN_FILL_INSERTION": true,
     "RUN_TAP_ENDCAP_INSERTION": true,
@@ -1410,22 +1410,22 @@ Now the full configuration file will be:
     "RUN_POST_GPL_DESIGN_REPAIR": true,
     "RUN_POST_CTS_RESIZER_TIMING": true,
     "DESIGN_REPAIR_BUFFER_INPUT_PORTS": true,
-    "FP_PDN_ENABLE_RAILS": true,
+    "PDN_ENABLE_RAILS": true,
     "RUN_ANTENNA_REPAIR": true,
     "RUN_FILL_INSERTION": true,
     "RUN_TAP_ENDCAP_INSERTION": true,
     "RUN_CTS": true,
     "RUN_IRDROP_REPORT": true,
 
     "//": "PDN configurations",
-    "FP_PDN_VOFFSET": 5,
-    "FP_PDN_HOFFSET": 5,
-    "FP_PDN_VWIDTH": 3.1,
-    "FP_PDN_HWIDTH": 3.1,
-    "FP_PDN_VSPACING": 15.5,
-    "FP_PDN_HSPACING": 15.5,
-    "FP_PDN_VPITCH": 180,
-    "FP_PDN_HPITCH": 180,
+    "PDN_VOFFSET": 5,
+    "PDN_HOFFSET": 5,
+    "PDN_VWIDTH": 3.1,
+    "PDN_HWIDTH": 3.1,
+    "PDN_VSPACING": 15.5,
+    "PDN_HSPACING": 15.5,
+    "PDN_VPITCH": 180,
+    "PDN_HPITCH": 180,
     "QUIT_ON_PDN_VIOLATIONS": false,
 
     "//": "Magic variables",
@@ -1449,13 +1449,13 @@ Now the full configuration file will be:
         "vssa1",
         "vssa2"
     ],
-    "FP_PDN_CORE_RING": 1,
-    "FP_PDN_CORE_RING_VWIDTH": 3.1,
-    "FP_PDN_CORE_RING_HWIDTH": 3.1,
-    "FP_PDN_CORE_RING_VOFFSET": 12.45,
-    "FP_PDN_CORE_RING_HOFFSET": 12.45,
-    "FP_PDN_CORE_RING_VSPACING": 1.7,
-    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "PDN_CORE_RING": 1,
+    "PDN_CORE_RING_VWIDTH": 3.1,
+    "PDN_CORE_RING_HWIDTH": 3.1,
+    "PDN_CORE_RING_VOFFSET": 12.45,
+    "PDN_CORE_RING_HOFFSET": 12.45,
+    "PDN_CORE_RING_VSPACING": 1.7,
+    "PDN_CORE_RING_HSPACING": 1.7,
     "CLOCK_PORT": "wb_clk_i",
     "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
     "MAGIC_DEF_LABELS": 0,
@@ -1853,7 +1853,7 @@ be:
     "RUN_POST_GPL_DESIGN_REPAIR": true,
     "RUN_POST_CTS_RESIZER_TIMING": true,
     "DESIGN_REPAIR_BUFFER_INPUT_PORTS": true,
-    "FP_PDN_ENABLE_RAILS": true,
+    "PDN_ENABLE_RAILS": true,
     "RUN_ANTENNA_REPAIR": true,
     "RUN_FILL_INSERTION": true,
     "RUN_TAP_ENDCAP_INSERTION": true,
@@ -1865,14 +1865,14 @@ be:
     },
 
     "//": "PDN configurations",
-    "FP_PDN_VOFFSET": 5,
-    "FP_PDN_HOFFSET": 5,
-    "FP_PDN_VWIDTH": 3.1,
-    "FP_PDN_HWIDTH": 3.1,
-    "FP_PDN_VSPACING": 15.5,
-    "FP_PDN_HSPACING": 15.5,
-    "FP_PDN_VPITCH": 180,
-    "FP_PDN_HPITCH": 180,
+    "PDN_VOFFSET": 5,
+    "PDN_HOFFSET": 5,
+    "PDN_VWIDTH": 3.1,
+    "PDN_HWIDTH": 3.1,
+    "PDN_VSPACING": 15.5,
+    "PDN_HSPACING": 15.5,
+    "PDN_VPITCH": 180,
+    "PDN_HPITCH": 180,
     "QUIT_ON_PDN_VIOLATIONS": false,
 
     "//": "Magic variables",
@@ -1906,13 +1906,13 @@ be:
         "vssa1",
         "vssa2"
     ],
-    "FP_PDN_CORE_RING": 1,
-    "FP_PDN_CORE_RING_VWIDTH": 3.1,
-    "FP_PDN_CORE_RING_HWIDTH": 3.1,
-    "FP_PDN_CORE_RING_VOFFSET": 12.45,
-    "FP_PDN_CORE_RING_HOFFSET": 12.45,
-    "FP_PDN_CORE_RING_VSPACING": 1.7,
-    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "PDN_CORE_RING": 1,
+    "PDN_CORE_RING_VWIDTH": 3.1,
+    "PDN_CORE_RING_HWIDTH": 3.1,
+    "PDN_CORE_RING_VOFFSET": 12.45,
+    "PDN_CORE_RING_HOFFSET": 12.45,
+    "PDN_CORE_RING_VSPACING": 1.7,
+    "PDN_CORE_RING_HSPACING": 1.7,
     "CLOCK_PORT": "wb_clk_i",
     "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
     "MAGIC_DEF_LABELS": 0,
@@ -2028,7 +2028,7 @@ The following edits are needed for this strategy:
     "RUN_POST_GPL_DESIGN_REPAIR": true,
     "RUN_POST_CTS_RESIZER_TIMING": true,
     "DESIGN_REPAIR_BUFFER_INPUT_PORTS": true,
-    "FP_PDN_ENABLE_RAILS": true,
+    "PDN_ENABLE_RAILS": true,
     "RUN_ANTENNA_REPAIR": true,
     "RUN_FILL_INSERTION": true,
     "RUN_TAP_ENDCAP_INSERTION": true,
@@ -2108,7 +2108,7 @@ So, the final config.json for the User Project's Wrapper will be:
     "RUN_POST_GPL_DESIGN_REPAIR": true,
     "RUN_POST_CTS_RESIZER_TIMING": true,
     "DESIGN_REPAIR_BUFFER_INPUT_PORTS": true,
-    "FP_PDN_ENABLE_RAILS": true,
+    "PDN_ENABLE_RAILS": true,
     "RUN_ANTENNA_REPAIR": true,
     "RUN_FILL_INSERTION": true,
     "RUN_TAP_ENDCAP_INSERTION": true,
@@ -2152,14 +2152,14 @@ So, the final config.json for the User Project's Wrapper will be:
     "PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 VPWR VGND"],
 
     "//": "PDN configurations",
-    "FP_PDN_VOFFSET": 5,
-    "FP_PDN_HOFFSET": 5,
-    "FP_PDN_VWIDTH": 3.1,
-    "FP_PDN_HWIDTH": 3.1,
-    "FP_PDN_VSPACING": 15.5,
-    "FP_PDN_HSPACING": 15.5,
-    "FP_PDN_VPITCH": 180,
-    "FP_PDN_HPITCH": 180,
+    "PDN_VOFFSET": 5,
+    "PDN_HOFFSET": 5,
+    "PDN_VWIDTH": 3.1,
+    "PDN_HWIDTH": 3.1,
+    "PDN_VSPACING": 15.5,
+    "PDN_HSPACING": 15.5,
+    "PDN_VPITCH": 180,
+    "PDN_HPITCH": 180,
     "QUIT_ON_PDN_VIOLATIONS": false,
 
     "//": "Magic variables",
@@ -2191,13 +2191,13 @@ So, the final config.json for the User Project's Wrapper will be:
         "vssa1",
         "vssa2"
     ],
-    "FP_PDN_CORE_RING": 1,
-    "FP_PDN_CORE_RING_VWIDTH": 3.1,
-    "FP_PDN_CORE_RING_HWIDTH": 3.1,
-    "FP_PDN_CORE_RING_VOFFSET": 12.45,
-    "FP_PDN_CORE_RING_HOFFSET": 12.45,
-    "FP_PDN_CORE_RING_VSPACING": 1.7,
-    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "PDN_CORE_RING": 1,
+    "PDN_CORE_RING_VWIDTH": 3.1,
+    "PDN_CORE_RING_HWIDTH": 3.1,
+    "PDN_CORE_RING_VOFFSET": 12.45,
+    "PDN_CORE_RING_HOFFSET": 12.45,
+    "PDN_CORE_RING_VSPACING": 1.7,
+    "PDN_CORE_RING_HSPACING": 1.7,
     "CLOCK_PORT": "wb_clk_i",
     "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
     "MAGIC_DEF_LABELS": 0,