Skip to content

use uncached ranges for esp32p4 #29

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
xobs wants to merge 2 commits into
base: master
Choose a base branch
from
Open

use uncached ranges for esp32p4 #29

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
415a8f8
use uncached ranges for esp32p4
xobs Nov 21, 2025
42a8733
shift memory range up to 0x8ff40020
xobs Nov 22, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ max-cpu-frequency = []

[profile.release]
codegen-units = 1
debug = false
debug = true
debug-assertions = false
incremental = false
lto = "fat"
Expand Down
4 changes: 2 additions & 2 deletions ld/esp32p4.x
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@

MEMORY {
/* Start 64k into the RAM region */
IRAM : ORIGIN = 0x4FF10000, LENGTH = 0x10000
/* Start 256k into the uncached RAM region */
IRAM : ORIGIN = 0x8FF50000, LENGTH = 0x10000
}

PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
Expand Down
4 changes: 2 additions & 2 deletions src/main.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ const _: [u8; 43776] = [0; core::mem::size_of::<Decompressor>()];
// ESP32-C6 | 0x4081_0000 | 0x4081_0000 | 0x4084_0000 | 0x4085_0000 | 0x4086_0000
// ESP32-C61 | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000 | 0x4083_8000 !! ROM data use starts at 0x4083EA70, so let's use H2's memory layout
// ESP32-H2 | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000 | 0x4083_8000 !! has smaller RAM, only reserve 32K for data
// ESP32-P4 | 0x4FF1_0000 | 0x4FF1_0000 | 0x4FF6_0000 | 0x4FF7_0000 | 0x4FFC_0000
// ESP32-P4 | 0x8FF4_0020 | 0x8FF4_0020 | 0x8FF6_0000 | 0x8FF7_0000 | 0x8FFC_0000 !! Uncached region

// "State" base address
#[cfg(feature = "esp32")]
Expand All @@ -55,7 +55,7 @@ const STATE_ADDR: usize = 0x4082_0000;
#[cfg(feature = "esp32h2")]
const STATE_ADDR: usize = 0x4082_0000;
#[cfg(feature = "esp32p4")]
const STATE_ADDR: usize = 0x4FF6_0000;
const STATE_ADDR: usize = 0x8FF6_0000;

// End of target memory configuration

Expand Down