Unstabilize CPU-related functionality, merge modules

esp-hal-embassy/src/executor/interrupt.rs

@@ -5,7 +5,7 @@ use core::{cell::UnsafeCell, mem::MaybeUninit};
 use embassy_executor::SendSpawner;
 use esp_hal::{
     interrupt::{self, software::SoftwareInterrupt, InterruptHandler},
-    Cpu,
+    system::Cpu,
 };
 use portable_atomic::{AtomicUsize, Ordering};
 

esp-hal-embassy/src/executor/thread.rs

@@ -5,7 +5,7 @@ use core::marker::PhantomData;
 use embassy_executor::Spawner;
 #[cfg(all(low_power_wait, multi_core))]
 use esp_hal::interrupt::software::SoftwareInterrupt;
-use esp_hal::{interrupt::Priority, Cpu};
+use esp_hal::{interrupt::Priority, system::Cpu};
 #[cfg(low_power_wait)]
 use portable_atomic::{AtomicBool, Ordering};
 

esp-hal/CHANGELOG.md

@@ -40,6 +40,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Removed features `psram-quad` and `psram-octal` - replaced by `psram` and the `ESP_HAL_CONFIG_PSRAM_MODE` (`quad`/`octal`) (#3001)
 - The `esp_hal::time` module no longer reexports `fugit` types (#3083)
 - The `system::RadioClockController` trait has been replaced by the `clock::RadioClockController` struct. (#3100)
+- The `Cpu` struct and contents of the `reset` and `cpu_control` modules have been moved into `cpu`. (#)
+- The `software_reset_cpu` now takes which CPU to reset as parameter. (#)
 
 - I2C: Async functions are postfixed with `_async`, non-async functions are available in async-mode (#3056)
 

esp-hal/src/analog/adc/riscv.rs

@@ -534,7 +534,7 @@ impl<ADCI> crate::private::Sealed for Adc<'_, ADCI, Blocking> {}
 
 impl<ADCI> InterruptConfigurable for Adc<'_, ADCI, Blocking> {
     fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
-        for core in crate::Cpu::other() {
+        for core in crate::system::Cpu::other() {
             crate::interrupt::disable(core, InterruptSource);
         }
         unsafe { crate::interrupt::bind_interrupt(InterruptSource, handler.handler()) };
@@ -643,7 +643,7 @@ where
     pub fn into_blocking(self) -> Adc<'d, ADCI, Blocking> {
         if asynch::release_async_adc() {
             // Disable ADC interrupt on all cores if the last async ADC instance is disabled
-            for cpu in crate::Cpu::all() {
+            for cpu in crate::system::Cpu::all() {
                 crate::interrupt::disable(cpu, InterruptSource);
             }
         }

esp-hal/src/assist_debug.rs

@@ -52,7 +52,7 @@ impl<'d> DebugAssist<'d> {
     /// handlers.
     #[instability::unstable]
     pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
-        for core in crate::Cpu::other() {
+        for core in crate::system::Cpu::other() {
             crate::interrupt::disable(core, Interrupt::ASSIST_DEBUG);
         }
         unsafe { crate::interrupt::bind_interrupt(Interrupt::ASSIST_DEBUG, handler.handler()) };

esp-hal/src/dma/mod.rs

@@ -66,9 +66,9 @@ use crate::{
     peripherals::Interrupt,
     soc::{is_slice_in_dram, is_valid_memory_address, is_valid_ram_address},
     system,
+    system::Cpu,
     Async,
     Blocking,
-    Cpu,
     DriverMode,
 };
 
@@ -1873,7 +1873,7 @@ where
         self.clear_in(EnumSet::all());
 
         if let Some(interrupt) = self.rx_impl.peripheral_interrupt() {
-            for core in crate::Cpu::other() {
+            for core in crate::system::Cpu::other() {
                 crate::interrupt::disable(core, interrupt);
             }
             unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) };
@@ -2168,7 +2168,7 @@ where
         self.clear_out(EnumSet::all());
 
         if let Some(interrupt) = self.tx_impl.peripheral_interrupt() {
-            for core in crate::Cpu::other() {
+            for core in crate::system::Cpu::other() {
                 crate::interrupt::disable(core, interrupt);
             }
             unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) };

esp-hal/src/ecc.rs

@@ -992,7 +992,7 @@ impl<Dm: DriverMode> Ecc<'_, Dm> {
     /// handlers.
     #[instability::unstable]
     pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
-        for core in crate::Cpu::other() {
+        for core in crate::system::Cpu::other() {
             crate::interrupt::disable(core, Interrupt::ECC);
         }
         unsafe { crate::interrupt::bind_interrupt(Interrupt::ECC, handler.handler()) };

esp-hal/src/gpio/mod.rs

@@ -717,7 +717,8 @@ pub(crate) fn bind_default_interrupt_handler() {
     }
     // The vector table doesn't contain a custom entry.Still, the
     // peripheral interrupt may already be bound to something else.
-    if interrupt::bound_cpu_interrupt_for(crate::Cpu::current(), Interrupt::GPIO).is_some() {
+    if interrupt::bound_cpu_interrupt_for(crate::system::Cpu::current(), Interrupt::GPIO).is_some()
+    {
         info!("Not using default GPIO interrupt handler: peripheral interrupt already in use");
         return;
     }
@@ -773,7 +774,7 @@ impl Io {
     /// `None`)
     #[instability::unstable]
     pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
-        for core in crate::Cpu::other() {
+        for core in crate::system::Cpu::other() {
             crate::interrupt::disable(core, Interrupt::GPIO);
         }
         self.set_interrupt_priority(handler.priority());

esp-hal/src/i2c/master/mod.rs

@@ -1332,7 +1332,7 @@ impl Info {
     }
 
     fn set_interrupt_handler(&self, handler: InterruptHandler) {
-        for core in crate::Cpu::other() {
+        for core in crate::system::Cpu::other() {
             crate::interrupt::disable(core, self.interrupt);
         }
         self.enable_listen(EnumSet::all(), false);
@@ -1342,7 +1342,7 @@ impl Info {
     }
 
     fn disable_interrupts(&self) {
-        crate::interrupt::disable(crate::Cpu::current(), self.interrupt);
+        crate::interrupt::disable(crate::system::Cpu::current(), self.interrupt);
     }
 }
 

esp-hal/src/i2s/master.rs

@@ -1518,7 +1518,7 @@ mod private {
 
     impl RegisterAccessPrivate for I2S0 {
         fn set_interrupt_handler(&self, handler: InterruptHandler) {
-            for core in crate::Cpu::other() {
+            for core in crate::system::Cpu::other() {
                 crate::interrupt::disable(core, Interrupt::I2S0);
             }
             unsafe { crate::peripherals::I2S0::steal() }.bind_i2s0_interrupt(handler.handler());
@@ -1627,7 +1627,7 @@ mod private {
     #[cfg(i2s1)]
     impl RegisterAccessPrivate for I2S1 {
         fn set_interrupt_handler(&self, handler: InterruptHandler) {
-            for core in crate::Cpu::other() {
+            for core in crate::system::Cpu::other() {
                 crate::interrupt::disable(core, Interrupt::I2S1);
             }
             unsafe { crate::peripherals::I2S1::steal() }.bind_i2s1_interrupt(handler.handler());

esp-hal/src/interrupt/riscv.rs

@@ -25,7 +25,7 @@ use super::InterruptStatus;
 use crate::{
     pac,
     peripherals::{Interrupt, INTERRUPT_CORE0},
-    Cpu,
+    system::Cpu,
 };
 
 /// Interrupt Error
@@ -560,7 +560,7 @@ mod vectored {
 #[cfg(not(plic))]
 mod classic {
     use super::{CpuInterrupt, InterruptKind, Priority};
-    use crate::{peripherals::INTERRUPT_CORE0, Cpu};
+    use crate::{peripherals::INTERRUPT_CORE0, system::Cpu};
 
     #[cfg_attr(place_switch_tables_in_ram, link_section = ".rwtext")]
     pub(super) static DISABLED_CPU_INTERRUPT: u32 = 0;
@@ -710,7 +710,7 @@ mod classic {
 #[cfg(plic)]
 mod plic {
     use super::{CpuInterrupt, InterruptKind, Priority};
-    use crate::{peripherals::PLIC_MX, Cpu};
+    use crate::{peripherals::PLIC_MX, system::Cpu};
 
     #[cfg_attr(place_switch_tables_in_ram, link_section = ".rwtext")]
     pub(super) static DISABLED_CPU_INTERRUPT: u32 = 31;

esp-hal/src/interrupt/software.rs

@@ -66,7 +66,7 @@ impl<const NUM: u8> SoftwareInterrupt<NUM> {
             _ => unreachable!(),
         };
 
-        for core in crate::Cpu::other() {
+        for core in crate::system::Cpu::other() {
             crate::interrupt::disable(core, interrupt);
         }
         unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()) };

esp-hal/src/interrupt/xtensa.rs

@@ -6,7 +6,7 @@ use xtensa_lx_rt::exception::Context;
 
 pub use self::vectored::*;
 use super::InterruptStatus;
-use crate::{pac, peripherals::Interrupt, Cpu};
+use crate::{pac, peripherals::Interrupt, system::Cpu};
 
 /// Interrupt Error
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]

esp-hal/src/lcd_cam/mod.rs

@@ -17,10 +17,9 @@ use crate::{
     lcd_cam::{cam::Cam, lcd::Lcd},
     peripheral::Peripheral,
     peripherals::{Interrupt, LCD_CAM},
-    system::GenericPeripheralGuard,
+    system::{Cpu, GenericPeripheralGuard},
     Async,
     Blocking,
-    Cpu,
 };
 
 /// Represents a combined LCD and Camera interface.
@@ -71,7 +70,7 @@ impl<'d> LcdCam<'d, Blocking> {
     /// handlers.
     #[instability::unstable]
     pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
-        for core in crate::Cpu::other() {
+        for core in crate::system::Cpu::other() {
             crate::interrupt::disable(core, Interrupt::LCD_CAM);
         }
         unsafe { crate::interrupt::bind_interrupt(Interrupt::LCD_CAM, handler.handler()) };

esp-hal/src/lib.rs

@@ -155,8 +155,6 @@ pub use esp_riscv_rt::{self, riscv};
 pub use xtensa_lx_rt::{self, xtensa_lx};
 
 // TODO what should we reexport stably?
-#[cfg(any(esp32, esp32s3))]
-pub use self::soc::cpu_control;
 #[cfg(efuse)]
 #[instability::unstable]
 #[cfg_attr(not(feature = "unstable"), allow(unused))]
@@ -186,6 +184,7 @@ pub mod peripheral;
 mod reg_access;
 #[cfg(any(spi0, spi1, spi2, spi3))]
 pub mod spi;
+pub mod system;
 pub mod time;
 #[cfg(any(uart0, uart1, uart2))]
 pub mod uart;
@@ -262,8 +261,6 @@ unstable_module! {
     pub mod parl_io;
     #[cfg(pcnt)]
     pub mod pcnt;
-    #[cfg(any(lp_clkrst, rtc_cntl))]
-    pub mod reset;
     #[cfg(rmt)]
     pub mod rmt;
     #[cfg(rng)]
@@ -277,8 +274,6 @@ unstable_module! {
     pub mod sha;
     #[doc(hidden)]
     pub mod sync;
-    #[cfg(any(dport, hp_sys, pcr, system))]
-    pub mod system;
     #[cfg(any(systimer, timg0, timg1))]
     pub mod timer;
     #[cfg(touch)]
@@ -294,6 +289,8 @@ unstable_module! {
 }
 
 /// State of the CPU saved when entering exception or interrupt
+#[instability::unstable]
+#[allow(unused_imports)]
 pub mod trapframe {
     #[cfg(riscv)]
     pub use esp_riscv_rt::TrapFrame;
@@ -404,97 +401,6 @@ pub mod __macro_implementation {
     pub use xtensa_lx_rt::entry as __entry;
 }
 
-/// Available CPU cores
-///
-/// The actual number of available cores depends on the target.
-#[derive(Debug, Copy, Clone, PartialEq, Eq, strum::FromRepr)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[repr(C)]
-pub enum Cpu {
-    /// The first core
-    ProCpu = 0,
-    /// The second core
-    #[cfg(multi_core)]
-    AppCpu = 1,
-}
-
-impl Cpu {
-    /// The number of available cores.
-    pub const COUNT: usize = 1 + cfg!(multi_core) as usize;
-
-    /// Returns the core the application is currently executing on
-    #[inline(always)]
-    pub fn current() -> Self {
-        // This works for both RISCV and Xtensa because both
-        // get_raw_core functions return zero, _or_ something
-        // greater than zero; 1 in the case of RISCV and 0x2000
-        // in the case of Xtensa.
-        match raw_core() {
-            0 => Cpu::ProCpu,
-            #[cfg(all(multi_core, riscv))]
-            1 => Cpu::AppCpu,
-            #[cfg(all(multi_core, xtensa))]
-            0x2000 => Cpu::AppCpu,
-            _ => unreachable!(),
-        }
-    }
-
-    /// Returns an iterator over the "other" cores.
-    #[inline(always)]
-    pub(crate) fn other() -> impl Iterator<Item = Self> {
-        cfg_if::cfg_if! {
-            if #[cfg(multi_core)] {
-                match Self::current() {
-                    Cpu::ProCpu => [Cpu::AppCpu].into_iter(),
-                    Cpu::AppCpu => [Cpu::ProCpu].into_iter(),
-                }
-            } else {
-                [].into_iter()
-            }
-        }
-    }
-
-    /// Returns an iterator over all cores.
-    #[inline(always)]
-    pub(crate) fn all() -> impl Iterator<Item = Self> {
-        cfg_if::cfg_if! {
-            if #[cfg(multi_core)] {
-                [Cpu::ProCpu, Cpu::AppCpu].into_iter()
-            } else {
-                [Cpu::ProCpu].into_iter()
-            }
-        }
-    }
-}
-
-/// Returns the raw value of the mhartid register.
-///
-/// Safety: This method should never return UNUSED_THREAD_ID_VALUE
-#[cfg(riscv)]
-#[inline(always)]
-fn raw_core() -> usize {
-    #[cfg(multi_core)]
-    {
-        riscv::register::mhartid::read()
-    }
-
-    #[cfg(not(multi_core))]
-    0
-}
-
-/// Returns the result of reading the PRID register logically ANDed with 0x2000,
-/// the 13th bit in the register. Espressif Xtensa chips use this bit to
-/// determine the core id.
-///
-/// Returns either 0 or 0x2000
-///
-/// Safety: This method should never return UNUSED_THREAD_ID_VALUE
-#[cfg(xtensa)]
-#[inline(always)]
-fn raw_core() -> usize {
-    (xtensa_lx::get_processor_id() & 0x2000) as usize
-}
-
 #[cfg(riscv)]
 #[export_name = "hal_main"]
 fn hal_main(a0: usize, a1: usize, a2: usize) -> ! {

esp-hal/src/otg_fs.rs

@@ -147,7 +147,7 @@ pub mod asynch {
     use procmacros::handler;
 
     use super::*;
-    use crate::Cpu;
+    use crate::system::Cpu;
 
     // From ESP32-S3 TRM:
     // Six additional endpoints (endpoint numbers 1 to 6), configurable as IN or OUT