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1. fpga-pc-uart fpga-pc-uart Public

   Demonstrates reliable data transfer between an FPGA and a computer (PC) via UART handshake protocol

   Verilog 1

2. rtl-design rtl-design Public

   RTL projects for various applications

   SystemVerilog

3. rtl-verif rtl-verif Public

   Projects focussing on RTL verification (UVM, SV, UVM Framework etc.,)

   SystemVerilog