v1.0

Changes;
* Major rebase of core implementation.
* Updates and fixes to match newer RISC-V ISA specs.
* Unify all variants into a single implementation with params.
* Slightly larger and slightly lower performance per cycle than previous version, but better verified and achieves a higher F-max.
* Re-add basic MMU.

Tests:
* RISC-V DV project sequences.
* Random instruction feed compared against reference checker.
* Boots 32-bit Linux 5.0 with atomic instruction emulation bootloader on MiniSpartan6+ (Xilinx XC6LX9).

README.md

@@ -1,39 +1,55 @@
 # RISC-V Core
 
-Github: http://github.com/ultraembedded/riscv
+Github: [http://github.com/ultraembedded/riscv](http://github.com/ultraembedded/riscv)
 
 A 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM.  
 This core has been tested against a co-simulation model and exercised on FPGA.
 
-**For a better tested, higher performance core which boots Linux, see my latest RISC-V core here;**
+**For a higher performance dual issue CPU with branch prediction, see my latest RISC-V core here;**
 [http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)
 
 ## Overview
 ![](doc/overview.png)
 
+## Features
+* 32-bit RISC-V ISA CPU core.
+* Support RISC-V integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
+* Supports user, supervisor and machine mode privilege levels.
+* Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.
+* Implements base ISA spec [v2.1](https://github.com/ultraembedded/riscv/blob/master/docs/riscv_isa_spec.pdf) and privileged ISA spec [v1.11](https://github.com/ultraembedded/riscv/blob/master/docs/riscv_privileged_spec.pdf).
+* Verified using [Google's RISCV-DV](https://github.com/google/riscv-dv) random instruction sequences using cosimulation against [C++ ISA model](https://github.com/ultraembedded/exactstep).
+* Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
+* Configurable number of pipeline stages and result forwarding options.
+* Synthesizable Verilog 2001, Verilator and FPGA friendly.
+* Coremark:  **2.94 CoreMark/MHz**
+* Dhrystone: **1.25 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration)
+* Want higher performance (**4.1CM/MHz** / **1.9DMIPS/MHz**) - see [my improved core](http://github.com/ultraembedded/biriscv).
+
+#### Configuration
+
+| Param Name                | Valid Range          | Description                                   |
+| ------------------------- |:--------------------:| ----------------------------------------------|
+| SUPPORT_SUPER             | 1/0                  | Enable supervisor / user privilege levels.    |
+| SUPPORT_MMU               | 1/0                  | Enable basic memory management unit.          |
+| SUPPORT_MULDIV            | 1/0                  | Enable HW multiply / divide (RV-M).           |
+| SUPPORT_LOAD_BYPASS       | 1/0                  | Support load result bypass paths.             |
+| SUPPORT_MUL_BYPASS        | 1/0                  | Support multiply result bypass paths.         |
+| SUPPORT_REGFILE_XILINX    | 1/0                  | Support Xilinx optimised register file.       |
+| EXTRA_DECODE_STAGE        | 1/0                  | Extra decode pipe stage for improved timing.  |
+| MEM_CACHE_ADDR_MIN        | 32'h0 - 32'hffffffff | Lowest cacheable memory address.              |
+| MEM_CACHE_ADDR_MAX        | 32'h0 - 32'hffffffff | Highest cacheable memory address.             |
+
 ## Directories
 
 | Name                | Contents                                            |
 | ------------------- | --------------------------------------------------- |
-| core/rv32i          | RISC-V pipelined RV32I CPU core (Verilog)           |
-| core/rv32i_spartan6 | RISC-V pipelined RV32I optimised for small Spartan6 |
-| core/rv32im         | RISC-V pipelined RV32IM CPU core (Verilog)          |
+| core/riscv          | RISC-V pipelined RV32IM CPU core (Verilog)          |
 | isa_sim             | Instruction set simulator (C)                       |
 | top_tcm_axi/src_v   | Example instance with 64KB DP-RAM & AXI Interfaces  |
 | top_tcm_axi/tb      | System-C testbench for the core                     |
-| top_cache_axi/src_v | Example instance with instruction and data caches.   |
+| top_cache_axi/src_v | Example instance with instruction and data caches.  |
 | top_cache_axi/tb    | System-C testbench for the core                     |
 
-## Core
-
-The core (riscv_core) contains;
-* RV32I or RV32IM support depending on core variant.
-* 5-stage in-order, single issue.
-* Modified Harvard architecture.
-* Custom bus interfaces which can be connected directly to either RAM or Instruction / Data cache.
-* Coremark:  **3.14 CoreMark/MHz**
-* Dhrystone: **1.35 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration)
-
 ## Example Core Instance (with TCM memory)
 
 The top (top_tcm_axi/src_v/riscv_tcm_top.v) contains;

core/rv32i/riscv_alu.v → core/riscv/riscv_alu.v

@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------
 //                         RISC-V Core
-//                            V0.9.8
+//                            V1.0
 //                     Ultra-Embedded.com
 //                     Copyright 2014-2019
 //
@@ -38,7 +38,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
 // SUCH DAMAGE.
 //-----------------------------------------------------------------
-
 module riscv_alu
 (
     // Inputs
@@ -50,8 +49,6 @@ module riscv_alu
     ,output [ 31:0]  alu_p_o
 );
 
-
-
 //-----------------------------------------------------------------
 // Includes
 //-----------------------------------------------------------------
@@ -80,7 +77,18 @@ wire [31:0]     sub_res_w = alu_a_i - alu_b_i;
 //-----------------------------------------------------------------
 always @ (alu_op_i or alu_a_i or alu_b_i or sub_res_w)
 begin
-   case (alu_op_i)
+    shift_right_fill_r = 16'b0;
+    shift_right_1_r = 32'b0;
+    shift_right_2_r = 32'b0;
+    shift_right_4_r = 32'b0;
+    shift_right_8_r = 32'b0;
+
+    shift_left_1_r = 32'b0;
+    shift_left_2_r = 32'b0;
+    shift_left_4_r = 32'b0;
+    shift_left_8_r = 32'b0;
+
+    case (alu_op_i)
        //----------------------------------------------
        // Shift Left
        //----------------------------------------------   
@@ -191,10 +199,9 @@ begin
        begin
             result_r      = alu_a_i;
        end
-   endcase
+    endcase
 end
 
 assign alu_p_o    = result_r;
 
-
 endmodule