Skip to content

yunsong1/FPGA-Interface

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

9 Commits
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Bus-debug

Simulation and debugging of communication interface module based on FPGA

interface state interface state
I2C alt text CAN alt text
SPI alt text AXI4 alt text
UART alt text Eth alt text
One-wire alt text HSST alt text
RS232 alt text LVDS alt text
USB alt text PCIE alt text

About

Communication-interface-simulation

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published