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27 Open 89 Closed
27 Open 89 Closed
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Issues list

[Bug]: Request textDocument/documentSymbol failed. bug Something isn't working
#131 opened Mar 19, 2025 by GaosongXu
[Bug]: 输出信息中有一些占位符没有被替换。Some placeholders are not substituted. bug Something isn't working
#130 opened Mar 17, 2025 by NormalAlkene
[Bug]:The values in netlists are bit-reversed. 网表中数值比特位反转 bug Something isn't working
#129 opened Mar 17, 2025 by NormalAlkene
[Bug]: bug Something isn't working
#128 opened Mar 16, 2025 by LFZhou2000
[Bug]: netlist生成有时无法正常工作 bug Something isn't working
#127 opened Mar 11, 2025 by XJ4505
[Bug]: wave viewer界面无法上下滑动 bug Something isn't working
#126 opened Mar 9, 2025 by Currort
希望vcd查看增加utf-8类型
#125 opened Mar 6, 2025 by Currort
[Bug]: 代码文档化不工作 bug Something isn't working
#124 opened Feb 28, 2025 by Liuliuliu7
[Bug]: DIGTAL IDE的模块树在特定条件下无法显示源文件 bug Something isn't working
#122 opened Feb 21, 2025 by YouXiaoquan
[Bug]: SV语法不高亮 bug Something isn't working
#121 opened Feb 20, 2025 by JunYCui
[Bug]: Errors happen when parsing c:/Users/Administrate/Desktop/xiangmu/cpu_prj master/FPGA/rtl/core/if id.v. Error: "RuntimeError: null function or function signature mismatch". Just propose a valuable issue in our github repo bug Something isn't working
#120 opened Feb 17, 2025 by SY-coder-creator
[new feature] 期望支持fst格式的波形显示
#119 opened Feb 13, 2025 by TimeKeepper
systemverilog的补全功能不太好用
#117 opened Feb 7, 2025 by lycheeonline
1
system verilog补全功能性能较差
#116 opened Feb 6, 2025 by Xoikter
2
使用unique case或者priority case时formatter问题
#115 opened Jan 22, 2025 by BrianLChen
期望能够release loongarch版本的lsp
#114 opened Jan 16, 2025 by cheungxi
关于插件分发的疑问
#113 opened Jan 16, 2025 by cheungxi
[0.4.0] iverilog存在bug
#112 opened Jan 2, 2025 by pikapuma
1
添加工程路径和添加一个新建工程的按钮
#111 opened Dec 26, 2024 by huanglaotou
[new feature]如果存在仿真器专属语法，就会导致自动格式化混乱 Backend Issues for which back-enders are responsible enhancement New feature or request Frontend Issues for which front-enders are responsible
#91 opened Oct 23, 2024 by Liyue-Cheng
[new feature] 关于波形显示的一些建议 enhancement New feature or request Frontend Issues for which front-enders are responsible
#71 opened May 24, 2024 by lancyjk
3
[new feature] 采用iverilog生成的VCD貌似无法解析仿真数据 enhancement New feature or request Frontend Issues for which front-enders are responsible
#70 opened May 23, 2024 by chesswei1
10
[new feature]网表优化与插入文档 enhancement New feature or request
#68 opened May 16, 2024 by lancyjk
1
[new feature] 功能建议-能增加点类似Verilog-Mode的功能么 Backend Issues for which back-enders are responsible enhancement New feature or request lang-server language server issues
#60 opened Apr 22, 2024 by qinyalei
[new feature]支持对verilator 的dpi-c机制的支持 Backend Issues for which back-enders are responsible enhancement New feature or request lang-server language server issues
#42 opened Dec 22, 2023 by CzealChen
ProTip! Exclude everything labeled bug with -label:bug.