SPI Protocol
SPI is a synchronous, full duplex main-subnode-based interface. The data from the main or the subnode is synchronized on the rising or falling clock edge. Both main and subnode can transmit data at the same time. The SPI interface can be either 3-wire or 4-wire.
Master: The controller of the communication process, typically a microcontroller. Slave: One or more devices that respond to the master’s commands.
- SClock - Generated by the master, this clock signal synchronizes data transmission. It specifies the clock frequency and polarity, and when the data bits will be transferred.
- Chip select - This control line selects the active slave device.
- main out, subnode in (MOSI) - This line transmits data from the master to the slave.
- main in, subnode out (MISO) - This line transmits data from the slave to the master, matching the voltage level used by the MOSI line.
Central to SPI’s operation is the clock polarity (CPOL) and clock phase (CPHA) settings, which define the timing relationship between the clock signal (SCLK) and the data lines.
Clock Polarity (CPOL): Indicates the idle state of the clock signal.
CPOL = 0 means the clock is low when idle
CPOL = 1 means the clock is high when idle
Clock Phase (CPHA): Determines which clock edge data is sampled.
CPHA = 0 sample data on the leading edge
CPHA = 1 sample data on the trailing edge.
In regular mode, an individual chip select for each subnode is required from the main. Once the chip select signal is enabled (pulled low) by the main, the clock and data on the MOSI/MISO lines are available for the selected subnode. If multiple chip select signals are enabled, the data on the MISO line is corrupted, as there is no way for the main to identify which subnode is transmitting the data.
The subnodes are configured such that the chip select signal for all subnodes is tied together and data propagates from one subnode to the next. In this configuration, all subnodes receive the same SPI clock at the same time. The number of clock cycles required to transmit data is proportional to the subnode position in the daisy chain.
https://www.analog.com/en/resources/analog-dialogue/articles/introduction-to-spi-interface.html