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Verilog: distinguish packed and unpacked arrays #412

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Merged
merged 5 commits into from
Mar 21, 2024
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This adds two new IDs to distinguish packed and unpacked arrays in the Verilog parse tree.

@kroening kroening force-pushed the verilog-array-types branch from 9f0614b to 1379aa5 Compare March 15, 2024 22:59
@kroening kroening marked this pull request as ready for review March 15, 2024 23:02
@kroening kroening force-pushed the verilog-array-types branch from 07af57a to cfde596 Compare March 15, 2024 23:15
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It is a bit surprising that this PR only adds KNOWNBUG tests. Is the case that with the new ability to distinguish we can just identify what we don't support, but add any new support?

else
array_subtype = array_type(src_subtype, element_type);

const exprt final_size_expr = from_integer(size, natural_typet());
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In #407 the type was changed to integer_typet. (And this is now a git conflict that requires resolving.)

@kroening kroening force-pushed the verilog-array-types branch from cfde596 to bd76093 Compare March 21, 2024 00:02
This adds two new IDs to distinguish packed and unpacked arrays in the
Verilog parse tree.
This removes the net_name rule, and makes the assignment in the
net_decl_assignment rule optional, to match SystemVerilog 1800-2017.
This moves the verilog_typecheckt::array_type method to
verilog_typecheck_exprt, together with the other type conversion methods.
@kroening kroening force-pushed the verilog-array-types branch from bd76093 to 0844c0b Compare March 21, 2024 00:09
@kroening kroening merged commit 8dbbbc0 into main Mar 21, 2024
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@kroening kroening deleted the verilog-array-types branch March 21, 2024 00:26
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2 participants