[WebAssembly] Combine any_true (setcc x, 0, eq) to not all_true

[badumbatish]

Fix a miss of further vectorization introduced in #50142 , where we can only achieve zext (xor (any_true), -1).

Now in test case issue50142, it's converted to all_true.

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[llvmbot]

@llvm/pr-subscribers-backend-webassembly

Author: jjasmine (badumbatish)

Changes

Fix a miss of further vectorization introduced in #50142 , where we can only achieve zext (xor (any_true), -1).

Now in test case issue50142, it's converted to all_true.

---

Full diff: https://github.com/llvm/llvm-project/pull/144741.diff

2 Files Affected:

• (modified) llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (+31)
• (added) llvm/test/CodeGen/WebAssembly/issue50142.ll (+20)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 3cd923c0ba058..84a18f74867a5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -19,6 +19,7 @@
 #include "WebAssemblyTargetMachine.h"
 #include "WebAssemblyUtilities.h"
 #include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
@@ -36,6 +37,7 @@
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetOptions.h"
+#include <iostream>
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-lower"
@@ -3248,6 +3250,35 @@ static SDValue performSETCCCombine(SDNode *N,
   ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
   SDLoc DL(N);
   EVT VT = N->getValueType(0);
+  //  N           LHS     LhsL        LhsLL    LhsLR   InnerCond RHS Cond
+  // setcc (iN (bitcast (setcc vNi1 (vNiY X), <vNiY 0>, eq)),     0, eq
+  // => all_true (vNi1 X)
+  if (DCI.isBeforeLegalize() && VT.isScalarInteger() && (Cond == ISD::SETEQ) &&
+      (isNullConstant(RHS)) && LHS->getOpcode() == ISD::BITCAST) {
+    SDValue LhsL = LHS.getOperand(0);
+    EVT LhsLType = LhsL.getValueType();
+    ISD::CondCode InnerCond = cast<CondCodeSDNode>(LhsL->getOperand(2))->get();
+    if (LhsL.getOpcode() == ISD::SETCC && InnerCond == ISD::SETEQ) {
+      SDValue LhsLL = LhsL.getOperand(0); // vNi1 X
+      SDValue LhsLR = LhsL.getOperand(1); // 0
+      unsigned NumElts = LhsLType.getVectorNumElements();
+      bool Vectorizable =
+          NumElts == 2 || NumElts == 4 || NumElts == 8 || NumElts == 16;
+      EVT Width = MVT::getIntegerVT(128 / NumElts);
+      // EVT LhsLLType = LhsLL.getValueType();
+
+      if (Vectorizable && LhsLR.getOpcode() == ISD::BUILD_VECTOR &&
+          LhsLType.isFixedLengthVector()) {
+        return DAG.getZExtOrTrunc(
+            DAG.getNode(
+                ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+                {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
+                 DAG.getSExtOrTrunc(LhsLL, DL,
+                                    LhsLType.changeVectorElementType(Width))}),
+            DL, MVT::i1);
+      }
+    }
+  }
 
   // setcc (iN (bitcast (vNi1 X))), 0, ne
   //   ==> any_true (vNi1 X)
diff --git a/llvm/test/CodeGen/WebAssembly/issue50142.ll b/llvm/test/CodeGen/WebAssembly/issue50142.ll
new file mode 100644
index 0000000000000..24ba941e76ee2
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/issue50142.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=wasm32-- -mattr=+simd128 | FileCheck --check-prefix=CHECK %s
+
+; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read)
+define hidden range(i32 0, 2) i32 @all_true(ptr noundef readonly captures(none) %a) local_unnamed_addr #0 {
+; CHECK-LABEL: all_true:
+; CHECK:         .functype all_true (i32) -> (i32)
+; CHECK: local.get 0
+; CHECK-NEXT: v128.load 0:p2align=0
+; CHECK-NEXT: i8x16.all_true
+; CHECK-NEXT:    # fallthrough-return
+; CHECK-NEXT: end_function 
+entry:
+  %0 = load <16 x i8>, ptr %a, align 1
+  %.fr = freeze <16 x i8> %0
+  %1 = icmp eq <16 x i8> %.fr, zeroinitializer
+  %2 = bitcast <16 x i1> %1 to i16
+  %3 = icmp eq i16 %2, 0
+  %conv3 = zext i1 %3 to i32
+  ret i32 %conv3
+}

[badumbatish]

@tlively hi, I saw you're one of the issue filers for #50142, I'm not sure who's the code reviewers for the webassembly components to review my code. Can i get some pointers on who to tag?

[dschuff]

@tlively is probably good (unless he wants to delegate that off), also @sparker-arm has been working on wasm SIMD recently.

[lukel97]

Can you precommit the test in this PR? I.e. rebase this so there's one commit adding the test without the changes, and another adding the changes to WebAssemblyISelLowering.cpp and the changes to the test case. That way you can see the diff in the PR

[badumbatish]

i updated the code, in the case of 4xi16, the fold doesn't work since i was targeting setcc

define i32 @all_true_4_i16(<4 x i16> %v) {
; CHECK-LABEL: all_true_4_i16:
; CHECK:         .functype all_true_4_i16 (v128) -> (i32)
; CHECK-NEXT:  # %bb.0:
; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK-NEXT:    i16x8.eq $push1=, $0, $pop0
; CHECK-NEXT:    i32x4.extend_low_i16x8_s $push2=, $pop1
; CHECK-NEXT:    v128.any_true $push3=, $pop2
; CHECK-NEXT:    i32.const $push4=, -1
; CHECK-NEXT:    i32.xor $push5=, $pop3, $pop4
; CHECK-NEXT:    i32.const $push6=, 1
; CHECK-NEXT:    i32.and $push7=, $pop5, $pop6
; CHECK-NEXT:    return $pop7
  %1 = icmp eq <4 x i16> %v, zeroinitializer
  %2 = bitcast <4 x i1> %1 to i4
  %3 = icmp eq i4 %2, 0
  %conv3 = zext i1 %3 to i32
  ret i32 %conv3
}

ok i just check the specs, haha there isn't any 4 x i16 in web assembly, will remove

[lukel97]

Thanks, this new approach looks good!

[lukel97]

LGTM, thanks! Although we should also wait for a WebAssembly maintainer to approve this too (this isn't my neck of the woods in LLVM!)

Can you also update your PR title to not reference the issue, but instead something like "[WebAssembly] Combine any_true (setcc x, 0, eq) to not all_true"?

We should also follow up on this to also handle:

• all_true (setcc x, 0, eq) -> not any_true
• any_true (setcc x, 0, ne) -> any_true
• all_true (setcc x, 0, ne) -> all_true

[badumbatish]

really sorry about the extra ping @tlively , can I please get the PR either approved or reviewed?

I think I can reuse some of the code for issue #145177. I just want to make sure the code structure is good before I base the new PR ontop of this PR

[badumbatish]

I've refactored, and added support and test case for three more patterns. This will fix #145177

all_true (setcc x, 0, eq) -> not any_true
any_true (setcc x, 0, ne) -> any_true
all_true (setcc x, 0, ne) -> all_true